LDPC Code Interleaving for Burst-Error-Resistant Decoding
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Solution Overview
Problem
Current data transmission using LDPC codes faces challenges in maintaining excellent communication quality, particularly in resisting burst errors and erasures, which deteriorate decoding performance and increase power consumption.
Innovation Solution
The implementation of data processing devices and methods that incorporate parity interleave and column twist interleaving techniques to rearrange LDPC code bits, allocating error-tolerant bits to strong symbol positions and error-prone bits to weak symbol positions, thereby enhancing resistance to burst errors and improving decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC code bits are transmitted without interleaving, then the transmission process is simple, but the system is vulnerable to burst errors and erasures that deteriorate decoding performance
Solution Approach 1:
The patent applies preliminary action by performing parity interleaving and column twist interleaving on LDPC code bits before transmission. This pre-arrangement of bits according to their error tolerance characteristics prepares the data structure in advance to resist burst errors and erasures, improving reliability without adding complexity during the actual transmission and decoding process
Solution Approach 2:
The patent implements local quality by differentiating the treatment of different LDPC code bits based on their error tolerance characteristics. Error-tolerant bits are allocated to strong symbol positions while error-prone bits are allocated to weak symbol positions through the interleaving process, creating a non-uniform but optimized distribution that enhances overall system reliability against burst errors
2Reliability
If LDPC code bits are allocated without considering error tolerance, then the allocation process is simple, but decoding performance deteriorates in channels with burst errors and erasures
Solution Approach 1:
The patent performs preliminary analysis of error tolerance characteristics of different LDPC code bits and pre-allocates them to appropriate symbol positions before transmission. This preliminary action ensures that error-tolerant bits are placed in strong symbol positions and error-prone bits in weak symbol positions, optimizing decoding performance without adding complexity during the decoding process itself
Solution Approach 2:
The patent applies local quality by treating different LDPC code bits differently based on their specific error tolerance characteristics. Through parity interleaving and column twist interleaving, the system creates a non-uniform allocation pattern where each bit position is optimized for its specific properties, thereby improving decoding performance in burst error and erasure channels
3Reliability
If no interleaving technique is used, then power consumption is low, but bit error rates increase in AWGN and Doppler frequency-shifted channels
Solution Approach 1:
The patent changes the structural parameters of the transmitted signal by applying parity interleaving and column twist interleaving. This reorganization of bit positions creates a more robust code structure that naturally resists burst errors and erasures, reducing bit error rates in AWGN and Doppler frequency-shifted channels without requiring additional power for retransmissions or complex error correction mechanisms
Data Source
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AI summary
The present technology relates to a data processing device and a data processing method so that an LDPC code with a good bit error rate is provided. An LDPC encoder encodes by an LDPC code whose code length is 16200 bits and code rate is 8/15. The LDPC code includes information bits and parity bits. A parity check matrix H includes an information matrix part corresponding to the information bits of the LDPC code and a parity matrix part corresponding to the parity bits. The information matrix part of the parity check matrix H is represented by a parity check matrix initial value table that indicates a position of an element 1 of the information matrix part for each 360 columns. The present technology is applicable to a case in which LDPC encoding and LDPC decoding are performed.