Multi-Mode LDPC Codec with Early Termination and Shared Hardware
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional LDPC codecs require a large number of iterations to achieve a given Bit Error Rate (BER) performance, leading to increased processing cycles and power consumption, especially in noisy channels, and lack a flexible hardware architecture to efficiently implement different WiMAX modes.
Innovation Solution
The proposed solution involves a low-complexity and multi-mode LDPC codec that partitions encoding and decoding operations into layers, sub-layers, and tasks, allowing for early termination of decoding operations and sharing of hardware resources between encoding and decoding, thereby reducing the number of iterations and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC codecs perform a large number of iterations to achieve given BER performance, then error correction reliability is improved, but processing time and power consumption increase
Solution Approach 1:
The patent partitions the parity-check matrix into multiple sub-matrices, enabling the decoding process to be divided into multiple stages. This segmentation allows the decoder to process different sub-matrices in sequence, reducing the computational complexity per iteration and enabling early termination when sufficient error correction is achieved, thus resolving the contradiction between reliability and processing time
Solution Approach 2:
The patent implements a dynamic iteration control mechanism where the number of iterations is adjusted based on the decoding progress and channel conditions. The decoder can terminate early when the error correction performance meets the required threshold, or continue with more iterations when higher reliability is needed, making the processing time adaptive rather than fixed
2Reliability
If conventional LDPC codecs perform more iterations to improve BER performance in noisy channels, then error correction reliability is improved, but power consumption increases
Solution Approach 1:
By dividing the parity-check matrix into sub-matrices, the patent enables the decoding process to be broken down into manageable stages. Each sub-matrix processing stage consumes a portion of the total power, and the system can stop after processing fewer stages if error correction is already sufficient, thereby reducing overall power consumption while maintaining required BER performance
Solution Approach 2:
The patent employs dynamic iteration control that adjusts the number of decoding iterations based on real-time decoding performance metrics. When the decoder achieves the target BER performance earlier than expected, it terminates the process, avoiding unnecessary power consumption from additional iterations and making power usage adaptive to actual channel conditions
3Speed
If LDPC codec uses dedicated hardware for encoding and decoding operations, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent designs a unified hardware architecture that can perform both encoding and decoding operations using the same core processing units. The same array of processing elements that execute decoding iterations can be reconfigured or repurposed to perform encoding operations, eliminating the need for separate dedicated hardware for each function and thereby reducing overall device complexity while maintaining processing speed
Data Source
AI summary
The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is implemented so that the hardware resources can be reused in different modes. In addition, memory access is achieved via routing networks with fixed interconnections and memory address generators, the complexity of the hardware implementation is reduced accordingly. Further, the present invention provides an early termination function with which the iterative operations can be terminated early when a threshold is reached so that the power consumption can be thus reduced. The hardware resources for early termination shares a part of hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced.