LDPC Codeword Interleaving and Constellation Mapping for Lower Thresholds
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Solution Overview
Problem
Existing broadcast communication standards face challenges in achieving optimal performance for LDPC coding, bit interleaving, and constellation mapping, leading to higher receiving thresholds at the receiving end.
Innovation Solution
An interleaving and mapping method for LDPC codewords is developed, involving multiple bit interleaving steps, constellation mapping, and optimized permutation orders and constellation diagrams to reduce the receiving threshold, along with a corresponding deinterleaving and demapping method for improved system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC coding, bit interleaving and constellation mapping are used independently, then system design flexibility is maintained, but receiving threshold performance deteriorates
Solution Approach 1:
The patent combines LDPC coding, bit interleaving, and constellation mapping into a unified joint design framework. The interleaving pattern and constellation mapping are specifically optimized to work together with the LDPC code structure, creating an integrated system that achieves lower receiving thresholds compared to independent design approaches.
Solution Approach 2:
The patent optimizes specific parameters including the interleaving pattern (column-wise with specific row permutations), constellation mapping rules (bit-to-symbol assignment), and their interaction with LDPC code parameters. These parameter optimizations are tailored to different code rates and block lengths to achieve optimal receiving threshold performance.
2Reliability
If targeted bit interleaving is designed for different LDPC codewords, then receiving threshold performance improves, but design complexity increases
Solution Approach 1:
The patent segments the LDPC codeword into information bits and parity bits, applying different interleaving strategies to each segment. The parity bits undergo column-wise interleaving with specific row permutations, while information bits are handled differently. This segmentation allows targeted optimization without requiring complete redesign of the entire system.
Solution Approach 2:
The patent performs preliminary optimization of the interleaving pattern and constellation mapping based on theoretical analysis before actual transmission. The design phase includes pre-calculating optimal parameters for different code rates and block lengths, so that during operation, the system can directly apply these pre-optimized configurations without real-time complex computations.
3Reliability
If multiple bit interleaving steps are applied, then receiving threshold is reduced, but processing complexity increases
Solution Approach 1:
The patent divides the interleaving process into distinct segments: first separating information and parity bits, then applying column-wise interleaving specifically to the parity bit portion with predetermined row permutations. This segmented approach allows each step to be optimized independently and executed efficiently without redundant operations.
Solution Approach 2:
The patent applies different interleaving qualities and methods to different parts of the codeword. The parity bits receive more aggressive column-wise interleaving with specific row permutations tailored to their error protection needs, while information bits use different handling. This local optimization achieves overall performance improvement without uniformly increasing complexity across all data.
Data Source
AI summary
An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving.