LDPC Codeword Interleaving for Lower Bit and Frame Error Rates

The patent divides the LDPC codeword into multiple bit groups and applies different interleaving strategies to different segments. The codeword is segmented into information bit groups and parity bit groups, with further subdivision into columns and rows for column-wise and row-wise interleaving operations respectively. This segmentation allows complex performance improvement to be achieved through manageable modular operations.

The patent introduces two-dimensional interleaving structure with column-wise and row-wise interleaving operations. Data is first interleaved column-wise within groups, then row-wise across groups, creating a multi-dimensional transformation that disperses error patterns more effectively than conventional one-dimensional approaches, thereby improving decoding performance.

The patent performs preliminary grouping and organization of bits into structured columns and rows before the actual interleaving operation. Bit groups are pre-arranged in a two-dimensional array structure with defined column and row indices, allowing the interleaving process to operate on already-organized data, which reduces processing time compared to unstructured approaches.

The patent extracts and separately processes information bits and parity bits into distinct groups. By separating the interleaving operations for information bit groups and parity bit groups, and further dividing into column-wise and row-wise operations, the system can process different portions independently and in parallel, reducing overall processing time while maintaining error performance benefits.

The patent segments the frame error protection task into multiple hierarchical levels: first dividing codeword bits into information and parity groups, then into columns and rows, and finally applying interleaving at each level. This multi-level segmentation transforms a single complex interleaving operation into several simpler, more manageable operations that collectively achieve superior frame error rate performance.

The patent employs two-dimensional row-wise and column-wise interleaving that transforms data in multiple dimensions. Column-wise interleaving operates vertically within groups while row-wise interleaving operates horizontally across groups, creating a multi-dimensional error dispersal pattern that significantly improves frame error rate without requiring excessively complex algorithms, as each dimensional operation remains relatively simple.