LDPC Codeword Bit Interleaving and Constellation Mapping Layout
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Solution Overview
Problem
Existing broadcast communication standards face challenges in achieving optimal performance for LDPC coding, bit interleaving, and constellation mapping, leading to higher receiving thresholds at the receiving end.
Innovation Solution
An interleaving and mapping method for LDPC codewords is developed, involving multiple bit interleaving steps, constellation mapping, and optimized permutation orders and constellation diagrams to reduce the receiving threshold, along with a deinterleaving and demapping method for improved system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC coding, bit interleaving and constellation mapping are used independently, then system design flexibility is maintained, but receiving threshold is high and system performance is suboptimal
Solution Approach 1:
The patent merges LDPC coding, bit interleaving, and constellation mapping into a unified joint design framework. The constellation mapping is specifically designed to match the LDPC code structure and bit interleaving pattern, creating an integrated system that optimizes overall performance rather than treating each component independently. This merging reduces the receiving threshold by ensuring coherent optimization across all processing stages.
Solution Approach 2:
The patent employs parameter optimization by adjusting constellation mapping parameters, bit interleaving patterns, and LDPC code parameters simultaneously. Through theoretical analysis and optimization, specific parameter configurations are identified that minimize the receiving threshold while maintaining system feasibility. This includes optimizing mapping rules and interleaving patterns to achieve the best trade-off between performance and complexity.
2Reliability
If targeted bit interleving is designed for different LDPC codewords through theoretical analysis and optimization, then receiving threshold is reduced, but design and implementation complexity increases
Solution Approach 1:
The patent segments the LDPC codeword into distinct parts (information bits and parity bits) and applies different interleaving and mapping strategies to each segment. This segmentation allows targeted optimization for each part's specific requirements while maintaining overall system coherence. The bit interleaving is designed with specific patterns that segment the code structure to achieve threshold reduction without requiring complete redesign of the entire system.
Solution Approach 2:
The patent performs preliminary theoretical analysis and optimization to establish optimal interleaving patterns and mapping rules before actual implementation. By pre-determining the optimal parameters and configurations through analysis, the implementation phase benefits from having already-optimized designs, reducing the complexity of real-time adjustments and simplifying the manufacturing and deployment process.
Data Source
AI summary
An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving.