LDPC Codeword Distribution Across Memory Dies to Reduce RBER
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Solution Overview
Problem
In solid-state memory devices, error correction codes are typically stored in a single memory die, leading to high raw bit error rates (RBER) when decoding, as the decoder must mitigate errors across all pages of NAND dies, which can result in inefficient error correction.
Innovation Solution
A codeword distribution manager is implemented to divide the codeword into portions and distribute them across multiple individual storage units, each with varying RBERs, allowing for averaging of errors and reduced overall RBER through parallel reads from multiple memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the LDPC codeword is completely stored in a single memory die, then the storage structure is simple, but the decoder must mitigate the worst raw bit error rate of all pages across all NAND dies, resulting in high RBER
Solution Approach 1:
The patent divides the LDPC codeword into multiple portions and distributes them across multiple memory dies or pages. Each portion is stored in a separate storage unit, allowing the system to avoid concentrating all data in a single location with potentially high error rates. This segmentation enables parallel reading from multiple units with lower individual RBERs.
Solution Approach 2:
The patent transitions from storing the entire codeword in a single memory die (one-dimensional storage) to distributing portions across multiple memory dies or pages (multi-dimensional storage). This dimensional expansion allows the system to leverage multiple storage units with different RBER characteristics, improving overall reliability.
2Productivity
If the codeword is stored in a single memory die, then the read operation is simple, but the error correction efficiency is reduced due to high RBER
Solution Approach 1:
The codeword is segmented into multiple portions that can be read in parallel from different memory units. This segmentation enables the error correction process to operate on multiple lower-error-rate portions simultaneously, improving overall correction efficiency while maintaining manageable read operations through the memory controller.
Solution Approach 2:
The patent merges the read operations of multiple memory units by coordinating parallel reads through the memory controller. This combining approach allows the system to aggregate data from multiple low-RBER sources, achieving better error correction efficiency without significantly complicating the read operation through centralized control.
3Reliability
If portions of the codeword are distributed across multiple storage units, then the RBER is reduced through error averaging, but the system complexity increases
Solution Approach 1:
The codeword distribution manager segments the codeword into portions and maps them to multiple storage units. This segmentation achieves error averaging across units with different RBERs, improving reliability. The segmentation is managed through software/firmware logic rather than hardware complexity, mitigating the increase in system complexity.
Solution Approach 2:
The codeword distribution manager acts as an intermediary layer between the host and the memory subsystem. It handles the complexity of distributing and managing codeword portions across multiple storage units, shielding the rest of the system from this complexity while achieving improved error correction reliability through diversified storage.
Data Source
AI summary
Embodiments are directed towards apparatuses, methods, and systems for a codeword distribution manager to divide a codeword into portions to be written to individual storage units and read from the corresponding different individual storage units to reduce a raw bit error rate (RBER) related to storage of the codeword. In embodiments, the codeword distribution manager is included in a memory controller and the plurality of individual storage units are coupled to the memory controller and include individual memory die or individual pages of a memory die. In embodiments, the codeword is a single codeword and includes encoded data and an error correction code. In some embodiments, the codeword includes a low density parity data check code (LDPC). Additional embodiments may be described and claimed.