LDPC Memory Controller Reconfiguration for Flash Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory controllers for flash memory devices, particularly MLC flash memories, require complex error correction mechanisms, leading to increased costs and inefficiencies due to different error correction ability requirements and design variations across products, necessitating a method to enhance data access control without introducing errors and allowing the same controller chip to be used across different products.
Innovation Solution
A method utilizing a low-density parity-check (LDPC) engine in the controller to decode and store error correction parameters, enabling the same controller chip to handle different error correction capabilities by switching between LDPC characteristic matrices, allowing the same controller chip to be applied to various products and improving memory apparatus performance without changing the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory controllers are equipped with powerful error correction mechanisms for MLC flash memories, then data correctness is ensured, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a universal LDPC engine that can handle multiple error correction configurations through software/firmware programming. The same hardware engine supports different LDPC characteristic matrices and parameter sets, allowing one controller design to serve multiple product requirements without hardware changes. This resolves the contradiction by providing powerful error correction capability while avoiding the need for multiple specialized controller designs.
Solution Approach 2:
The patent enables dynamic configuration of the LDPC engine by storing multiple sets of error correction parameters in non-volatile memory. The controller can switch between different LDPC characteristic matrices and parameter sets based on the specific memory device being accessed. This dynamic adaptability allows the system to provide appropriate error correction strength for each device without permanently increasing hardware complexity.
2Adaptability or versatility
If different error correction designs are implemented for different products, then specific product requirements are met, but manufacturing cost and design time increase
Solution Approach 1:
The patent creates a universal controller platform with an LDPC engine that can be programmed via software/firmware to support different error correction configurations. Multiple sets of LDPC parameters and characteristic matrices are stored in non-volatile memory, allowing the same hardware to adapt to different product requirements. This eliminates the need to manufacture different hardware versions for different products, significantly reducing manufacturing costs while maintaining product-specific optimization.
Solution Approach 2:
The patent implements flexibility by storing multiple sets of error correction parameters (different LDPC characteristic matrices, code rates, and configuration values) in non-volatile memory. The controller selects and switches between these parameter sets based on the specific memory device being accessed. This parameter-based configuration approach allows a single controller design to meet diverse product requirements without requiring different hardware implementations.
3Ease of manufacture
If the same controller chip is used across different products, then manufacturing cost is reduced, but adaptability to different error correction requirements decreases
Solution Approach 1:
The patent enables the same controller chip to adapt to different error correction requirements through dynamic configuration. Multiple sets of LDPC parameters and characteristic matrices are stored in non-volatile memory within the controller. The system can switch between these pre-stored configurations based on the specific memory device being accessed, providing the flexibility needed for different products while maintaining a standardized hardware platform.
Solution Approach 2:
The patent introduces non-volatile memory as an intermediary layer between the standardized LDPC engine hardware and the diverse product requirements. This intermediary stores multiple sets of configurable parameters and characteristic matrices, allowing the fixed hardware to achieve variable behavior. The non-volatile memory acts as a configuration repository that enables the same controller chip to serve different applications with different error correction needs.
Data Source
AI summary
A method for controlling a memory apparatus and the associated memory apparatus thereof and the associated controller thereof are provided, where the method includes: reading encoded data of a second set of error correction configuring parameters from a system block, and utilizing an LDPC engine to decode the encoded data to obtain the second set of error correction configuring parameters, where the LDPC engine stores a first set of error correction configuring parameters, and during decoding the encoded data, the LDPC engine performs decoding corresponding to a first LDPC characteristic matrix based on the first set of error correction configuring parameters; and controlling the LDPC engine to perform operations corresponding to a second LDPC characteristic matrix based on the second set of error correction configuring parameters in RAM, in order to make the LDPC engine be equipped with new encoding and decoding capabilities corresponding to the second LDPC characteristic matrix.