LDPC Convolutional Encoding for Multi-Rate Error Correction

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Solution Overview

Problem

Current LDPC-CC encoders and decoders face challenges in supporting multiple coding rates with low computational complexity while maintaining high received data quality, as existing methods either increase computational complexity or compromise on data quality.

Innovation Solution

The proposed solution involves an LDPC-CC encoder and decoder configuration that uses a parity check polynomial to set coding rates, employing a coding rate setting section, computation sections, a parity computing section, and an adding section for encoding, and a log likelihood ratio setting section and computation processing section for decoding, allowing for belief propagation based on a parity check matrix.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If puncturing processing is used to adjust LDPC code block length to match variable-length frames, then adaptability to variable-length transmission is improved, but coding rate changes and redundant sequence transmission occur

Engineering Contradiction:
Improveadaptability to variable-length transmissionVSAvoidredundant sequence transmission
Core Design Contradiction:
Adaptability or versatilityVSLoss of information

Solution Approach 1:

The patent employs a time-varying periodic parity check matrix where the matrix pattern changes periodically over time according to the formula H(t) = H(t mod g), where g is the period. This dynamic structure allows the encoder to adapt to variable-length frames without requiring puncturing or padding, as the time-varying nature naturally accommodates different transmission lengths while maintaining a fixed coding rate.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If multiple LDPC code configurations are used to support multiple coding rates, then coding rate versatility is improved, but device complexity increases

Engineering Contradiction:
Improvesupport for multiple coding ratesVSAvoidencoder and decoder complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent designs a universal time-varying LDPC-CC system where a single encoder and decoder structure supports multiple coding rates (1/2, 2/3, 3/4, etc.) by adjusting the parity check polynomial parameters. The same hardware/software implementation can operate at different coding rates by changing the polynomial coefficients, eliminating the need for multiple dedicated code configurations and reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent enables switching between different coding rates by modifying the parameters of the parity check polynomial rather than changing the entire code structure. The polynomial form remains consistent, but the specific coefficients and exponents are adjusted according to the desired coding rate, allowing flexible rate adaptation with minimal computational overhead.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If simple LDPC-CC encoder structure is used, then ease of implementation is improved, but support for multiple coding rates with low complexity is not achieved

Engineering Contradiction:
Improveencoder implementation simplicityVSAvoidmulti-coding rate support
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent introduces time-varying periodicity into the simple LDPC-CC encoder structure, where the parity check matrix pattern cycles through different configurations based on time index t. This dynamic element allows the simple base structure to achieve multiple coding rate support without increasing fundamental complexity, as the time-varying behavior is generated through systematic parameter variation rather than additional hardware.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8612838B2Convolutional code encoding method
Publication Date: 2013.12.17 PANASONIC HOLDINGS CORP
  • US8612838B2 patent drawing
  • US8612838B2 patent drawing
  • US8612838B2 patent drawing

AI summary

An encoder and decoder using LDPC-CC (Low Density Parity Check-Convolutional Codes). An encoding rate setting unit sets an encoding rate (s−1)/s (s=z), and an information creating unit sets information including from information Xs,i to information Xz−1,i to zero. A first information computing unit receives information X1,i at time point i to compute the X1(D) term of a formula. A second information computing unit receives information X2,i at time point i to compute the X2(D) term of the formula. A third information computing unit receives information X3,i at time point i to compute the X3(D) term of the formula. A parity computing unit receives parity Pi−1 at time point i−1 to compute the P(D) of the formula. The exclusive OR of the results of the computation is obtained as parity Pi at time i.