LDPC Decoder Cyclic Comparison for Arbitrary CNU Inputs

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Solution Overview

Problem

Conventional LDPC decoder technologies face performance loss and increased hardware complexity due to the Min-Sum algorithm, particularly in handling arbitrary input numbers for Check Node Units (CNUs), leading to slower operation speeds and resource consumption.

Innovation Solution

A cyclic comparison method for LDPC decoders that reduces calculations by using a sequence of level sequences, where k input elements form first, second, and third level sequences, with comparisons until identical outputs are determined, requiring only k×┌log2(k−1)┐ comparisons, allowing for efficient processing of any input number.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional comparison methods are used in LDPC decoders, then the decoding accuracy can be maintained, but the number of comparisons increases with input size, leading to increased hardware complexity and slower operation speed

Engineering Contradiction:
Improvedecoding accuracyVSAvoidhardware complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The comparison operation is segmented into multiple levels (first level sequences, second level sequences, third level sequences, and final level sequences). Each level processes a subset of the input elements, dividing the overall comparison task into manageable segments that can be executed in parallel, thereby reducing hardware complexity while maintaining decoding accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the traditional one-dimensional comparison approach into a multi-dimensional hierarchical structure. By organizing comparisons across multiple levels and dimensions, the algorithm reduces the total number of comparisons needed from O(k) to O(k×┌log2(k−1)┐), effectively adding dimensional organization to the comparison process.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the input number to CNU increases, then the decoder can handle more complex codes, but the number of comparisons increases, slowing down the operation speed

Engineering Contradiction:
Improveinput number handlingVSAvoidoperation speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent implements a dynamic comparison algorithm that adapts to the input size k. The number of comparison levels and elements processed at each level dynamically adjusts based on the input parameters, allowing the system to efficiently handle varying input sizes without linearly increasing the comparison count, thus maintaining operation speed while improving adaptability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The algorithm performs preliminary organization of input elements into level sequences before the actual comparison process. By pre-organizing the data structure and identifying potential matches in advance, the system reduces the number of comparisons needed during the decoding process, enabling faster operation even with increased input numbers.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If more comparators are added to handle larger input numbers, then the decoder can process more complex codes, but the resource consumption increases

Engineering Contradiction:
Improveinput number handlingVSAvoidresource consumption
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The hierarchical comparison algorithm creates a universal framework that can handle any input size k using the same basic comparison units. The same comparator circuits and logic structures are reused across multiple levels and iterations, allowing the system to process varying input sizes without requiring proportionally more hardware resources, thus reducing overall resource consumption while maintaining versatility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7966543B2Cyclic comparison method for low-density parity-check decoder
Publication Date: 2011.06.21 NAT CHIAO TUNG UNIV
  • US7966543B2 patent drawing
  • US7966543B2 patent drawing
  • US7966543B2 patent drawing

AI summary

A cyclic comparison method for an LDPC decoder. The nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first level sequences. Next, pairs of two elements selected from the k elements are used to form k second level sequences. The preceding step is repeated k×┌log2(k−1)┐ times to obtain k output results. Either of one first level sequences and one output results contains (k−1) elements. The first level sequences are compared with the output results to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new output results. The cyclic comparison method of the present invention needs only k×┌log2(k−1)┐ comparisons to obtain output results. Thus, the present invention can reduce the number of basic operations and can apply to any input number.