Column-Layered LDPC Decoder With 2-Bit Lookup-Table Messages
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Solution Overview
Problem
Conventional column-layered LDPC decoding schemes for flash memory devices require complex hardware and high manufacturing costs due to the need for multiple bit representations of messages, leading to increased error correction complexity and performance losses.
Innovation Solution
A lookup table-based variable node unit (VNU) and check node unit (CNU) architecture that uses reduced message sizes (2-bit messages) and count storage to reconstruct check-to-variable messages, reducing memory usage and complexity while maintaining error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional column-layered LDPC decoding schemes use multiple bit representations (min1, min2, index) for messages, then error correction performance is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts only the essential information needed for error correction by using a single minimum value (min1) instead of multiple values (min1, min2, index). This extraction principle reduces the message representation from multiple bits to a single magnitude value, significantly simplifying the hardware while maintaining adequate error correction performance.
Solution Approach 2:
The patent employs simpler, less expensive message representations that can be discarded and regenerated each iteration. By using reduced-precision messages (single magnitude value instead of multiple values with indices), the system trades message detail for hardware simplicity, achieving cost-effective error correction.
2Reliability
If 4-7 bit messages are used to achieve satisfactory error correction performance, then reliability is improved, but manufacturing cost increases due to expensive components
Solution Approach 1:
The patent uses simplified message representations requiring fewer bits, enabling implementation with cheaper components. By reducing message precision from 4-7 bits to fewer bits per message element, the system eliminates the need for expensive integer adders, comparators, and converters, achieving cost-effective manufacturing.
Solution Approach 2:
The patent changes the parameter of message precision from high (4-7 bits) to lower precision. This parameter change allows the use of simpler arithmetic operations and less complex hardware components, directly reducing manufacturing cost while maintaining acceptable error correction performance through the column-layered processing structure.
3Productivity
If column-layered schemes process all check nodes simultaneously, then productivity is improved, but device complexity increases due to complex hardware requirements
Solution Approach 1:
The patent segments the check node processing into column layers, where each layer processes a subset of check nodes simultaneously. This segmentation enables parallel processing (improving throughput) while keeping each processing unit simpler than a fully simultaneous all-check-node processor, thus managing hardware complexity.
Solution Approach 2:
The patent implements dynamic processing where message updates occur in stages across multiple column layers rather than all at once. This dynamic approach allows the system to achieve high throughput through pipelined parallel processing while using manageable hardware resources in each processing stage.
Data Source
AI summary
In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.