LDPC Decoder Architecture for 3D NAND Error Correction
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Solution Overview
Problem
The increasing error probability in three-dimensional NAND memory due to the transition from single-level cells to multi-level cells, such as TLC and QLC, is not adequately addressed by traditional error correction codes like BCH, necessitating improved decoder architectures for LDPC codes to enhance throughput and reduce resource utilization.
Innovation Solution
A decoder architecture is implemented with check and variable node updating circuits, utilizing first and second updating units in sequential connections, and shifting and delaying units to efficiently update check and variable node messages, optimizing the decoding process for LDPC codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction codes like BCH are used in three-dimensional NAND memory, then the implementation is simple, but the error correction capability is insufficient due to increasing error probability in multi-level cells
Solution Approach 1:
The decoder architecture is segmented into multiple updating units (first updating unit, second updating unit, third updating unit) that process different aspects of the decoding operation separately. Each unit handles specific message passing tasks between check nodes and variable nodes, allowing the complex LDPC decoding process to be divided into manageable, specialized components that can be implemented efficiently in hardware.
Solution Approach 2:
The patent introduces a hierarchical structure with multiple levels of updating units organized in parallel stages. This multi-dimensional arrangement allows simultaneous processing of multiple message updates across different levels, transforming the sequential complexity into parallel spatial organization, thereby improving throughput while maintaining manageable complexity at each level.
2Reliability
If LDPC codes are implemented with comprehensive check and variable node updating circuits, then the error correction capability is enhanced, but the resource utilization increases
Solution Approach 1:
Multiple updating units are merged into a unified decoder architecture where first, second, and third updating units work together in coordinated stages. The merging of these functional units allows shared resources and optimized message passing pathways, reducing overall resource utilization compared to implementing separate complete decoding circuits for each function.
Solution Approach 2:
The updating units perform partial decoding operations at each stage rather than complete decoding in a single unit. Each updating unit processes a subset of the total message passing requirements, and the cumulative effect of multiple partial actions achieves the complete error correction function with reduced resource demands at each individual stage.
3Quantity of substance
If sequential updating units are used in the decoder architecture, then the resource utilization is reduced, but the throughput decreases
Solution Approach 1:
The decoder implements periodic action through multi-stage updating units that operate in sequential batches. Each updating unit processes messages in periodic cycles, with the first updating unit completing its stage, then the second updating unit processing, and so on. This periodic staged processing allows efficient resource utilization while maintaining acceptable throughput through systematic rotation of active processing units.
Solution Approach 2:
Messages are preliminarily processed by early updating units before being passed to subsequent updating units. The first updating unit performs preliminary message updates and passes results to the second updating unit, which performs further preliminary processing before final decoding. This preliminary action at each stage prepares data for efficient subsequent processing, optimizing the balance between resource usage and throughput.
Data Source
AI summary
The present disclosure provides a decoder including: a check node updating circuit comprising first updating units of a levels, wherein the first updating unit of each level is connected sequentially, the first updating unit of a first level is connected with the first updating unit of a-th level; and a variable node updating circuit connected with the check node updating circuit, the variable node updating circuit comprises second updating units of a levels, wherein the second updating unit of each level is connected sequentially, the second updating unit of a first level is connected with the second updating unit of a-th level.