Adaptive LDPC Decoder Scheduling for Faster Convergence
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Solution Overview
Problem
Conventional LDPC decoders in flash memory devices have a static scheduling approach that affects data throughput, cost, and power consumption due to suboptimal convergence rates during error correction decoding.
Innovation Solution
An adaptive scheduling method is introduced for LDPC decoders, where the order of processing nodes is dynamically adjusted based on reliability values and unsatisfied parity check equations, allowing for a second schedule to be generated during decoding iterations to prioritize nodes with low reliability for initial processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a static pre-computed schedule is used for processing variable nodes, then the decoder structure is simple and easy to implement, but the convergence rate is suboptimal affecting data throughput
Solution Approach 1:
The patent applies dynamics by transitioning from a static pre-computed schedule to a dynamic adaptive schedule that changes during decoding iterations. The schedule is updated based on reliability values and unsatisfied parity check equations, allowing the processing order to adapt to the actual decoding state and improve convergence rate without requiring a completely complex redesign of the decoder architecture.
Solution Approach 2:
The patent changes the parameter of processing order by generating updated schedules that reorder variable node processing based on reliability metrics. This parameter change allows critical nodes with low reliability to be processed earlier in subsequent iterations, improving convergence while maintaining a manageable decoder structure through systematic reordering rather than architectural overhaul.
2Use of energy by stationary object
If a static pre-computed schedule is used for processing variable nodes, then the implementation is straightforward, but power consumption is higher due to slower convergence
Solution Approach 1:
The patent applies preliminary action by computing reliability values and generating updated schedules in advance of each decoding iteration. This preparation allows the decoder to immediately process nodes in the optimal order without runtime delays, reducing the number of iterations needed and thereby lowering power consumption while maintaining relatively simple implementation through pre-computation.
Solution Approach 2:
The patent implements feedback by using reliability values and unsatisfied parity check results from previous iterations to generate updated processing schedules. This feedback mechanism enables the decoder to learn from past performance and adjust its processing order accordingly, improving convergence efficiency and reducing power consumption without significantly complicating the implementation.
3Productivity
If nodes are processed in a fixed order, then the decoding process is simple to control, but erroneous nodes take longer to correct affecting overall decoding speed
Solution Approach 1:
The patent applies local quality by treating different variable nodes differently based on their individual reliability values. Nodes with low reliability are identified and prioritized for earlier processing in updated schedules, while high-reliability nodes maintain their original processing order. This localized adjustment improves decoding speed by focusing computational effort where it is most needed without requiring complete restructuring of the scheduling system.
Data Source
AI summary
A decoder includes a processor and a scheduler coupled to the processor. The processor is configured to process a set of nodes related to a representation of a codeword during a first decode iteration. The nodes are processed in a first order. The scheduler is configured to generate a schedule that indicates a second order of the set of nodes. The second order is different from the first order.