Bit-Flipping LDPC Decoder With Adaptive Threshold Convergence
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Solution Overview
Problem
Existing bit-flipping decoders in non-volatile memory devices, such as NAND flash, face inefficiencies in convergence and power consumption due to suboptimal error correction capabilities, which limits throughput and increases energy use.
Innovation Solution
The method improves convergence of bit-flipping decoders by dynamically updating the flipping threshold based on specific rules and iteration stages, optimizing the bit-flipping process to enhance throughput and reduce power consumption, particularly by employing adaptive flipping thresholds and iterative decoding algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional bit-flipping decoding algorithms are used, then error correction capability is maintained, but convergence speed is slow and power consumption is high
Solution Approach 1:
The patent implements dynamic threshold adjustment where the flipping threshold is adapted based on the current decoding stage and syndrome weight. The threshold transitions from an initial conservative value to progressively lower values across decoding stages, allowing the decoder to be more aggressive in later stages when closer to convergence, thereby reducing total iterations and power consumption
Solution Approach 2:
The patent changes the flipping threshold parameter dynamically during the decoding process. The threshold is updated based on the syndrome weight and current stage, transforming a static parameter into a dynamic one that adapts to the decoding progress, enabling faster convergence without increasing power consumption
2Reliability
If multiple decoding iterations are performed, then error correction accuracy is improved, but throughput is reduced
Solution Approach 1:
The patent performs preliminary actions by computing syndrome weights and selecting appropriate threshold values before each flipping operation. This preliminary preparation allows the decoder to make more informed decisions about which bits to flip, reducing the number of iterations needed to achieve convergence and thereby improving throughput while maintaining accuracy
3Device complexity
If a fixed flipping threshold is used, then implementation complexity is reduced, but convergence performance deteriorates
Solution Approach 1:
The patent segments the decoding process into multiple stages, each with its own threshold adjustment strategy. The first stage uses one set of threshold rules, while subsequent stages use different rules, allowing the system to balance complexity and performance by applying different levels of sophistication at different points in the decoding process
Data Source
AI summary
Disclosed are devices, systems and methods improving the convergence of a bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of a low-density parity-check code and provided to a communication channel prior to reception by the bit-flipping decoder, and performing a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages. In some embodiments, performing a single decoding iteration includes computing a metric corresponding to a single column of the parity check matrix, flipping at least one bit in the single column upon a determination that the metric exceeds a flipping threshold, computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and updating the flipping threshold upon a determination that the syndrome is not zero.