LDPC Decoder Address Control for Arbitrary Coding Rates
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Solution Overview
Problem
Existing LDPC codes decoders struggle to decode codes with arbitrary coding rates without changing the circuit configuration and face inefficiencies in processing throughput and error detection, particularly in handling different check matrices and coding rates.
Innovation Solution
A low-density parity check (LDPC) codes decoder is designed with a decoding control section that manages channel data and generates addresses for parallel column and row processing, utilizing a permutation matrix and base matrix information to iterate decoding processes, and includes features for invalidating processing based on validity flags and priority information to optimize throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fully parallel design is used to achieve high throughput (1 Gb/s), then processing speed is improved, but the decoder cannot handle LDPC codes with different check matrices
Solution Approach 1:
The patent introduces dynamic control mechanisms that allow the decoder configuration to change based on the input code requirements. Control signals dynamically adjust the operation of processing units and memory access patterns, enabling the same hardware to adapt to different check matrices while maintaining parallel processing efficiency
Solution Approach 2:
The decoder is designed with universal processing units that can handle multiple types of LDPC codes. By using configurable control logic and parameter storage, the same hardware structure performs decoding for different check matrices, achieving multi-functionality without sacrificing throughput
2Reliability
If the circuit configuration is fixed for a specific coding rate, then decoding accuracy is improved, but the decoder cannot decode codes with different coding rates
Solution Approach 1:
The patent implements parameter storage units that hold configuration data for different coding rates. By changing control parameters such as iteration counts, processing unit activation patterns, and memory access sequences, the decoder maintains optimized decoding accuracy for each coding rate while being able to switch between different rates
3Productivity
If parallel processing is implemented to improve throughput, then processing speed is improved, but device complexity increases
Solution Approach 1:
The decoder is divided into multiple independent processing units that work in parallel. Each unit handles a portion of the decoding task, and their results are combined. This segmentation enables throughput improvement while keeping individual unit complexity manageable
Solution Approach 2:
Multiple processing units share common resources such as control logic, parameter storage, and output aggregation circuits. By merging these shared components, the patent reduces overall device complexity while maintaining the benefits of parallel processing
Data Source
AI summary
A low density parity check codes decoder decodes an LDPC code with an arbitrary coding rate by the same configuration. The low density parity check codes decoder enables decoding of an LDPC code constituted by a base matrix of Mbmax rows and Nbmax columns and a permutation matrix as an element of the base matrix. It stores therein Mbmax×Nbmax validity/invalidity flags, shift amounts of valid permutation matrices, a permutation matrix size in a processing target code, and the number of rows of a base matrix in the processing target code, determined depending on a check matrix for the processing target LDPC code, and generates column addresses and a row address to be given to column processing calculation sections and a row processing calculation section that perform calculation in accordance with a BP algorithm by utilizing the stored information, so that it can process an LDPC code for a smaller base matrix than the aforementioned base matrix as well.