LDPC Memory Decoder Using Classifier-Trained Bit-Flipping Rules
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Solution Overview
Problem
NAND flash-based storage devices face challenges with higher costs, shorter usable lifespan, and decreased data reliability due to fabrication process limitations, necessitating a more powerful error correction code to improve data integrity and performance.
Innovation Solution
A semiconductor memory system and operating method that includes a controller with a training data storage, classifier trainer, and decoder, which automatically optimizes bit-flipping (BF) rules for LDPC codes using a random-forest classifier trained on simulation data, enabling better decoding performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BCH error correction codes are used, then device complexity is lower, but data reliability and error correction capability are insufficient for advanced NAND flash processes
Solution Approach 1:
The patent changes the fundamental parameters of error correction by transitioning from BCH codes to LDPC codes, which have different structural parameters (parity-check matrix density, code rate, block length) that provide superior error correction capability for advanced NAND flash processes while managing complexity through optimized implementations
Solution Approach 2:
The patent replaces the traditional BCH error correction mechanism with an LDPC-based belief propagation decoding mechanism, substituting one error correction paradigm with another that is better suited for the specific challenges of advanced NAND flash, achieving improved reliability through a different computational approach
2Reliability
If more powerful error correction codes like LDPC are implemented, then data integrity improves, but decoding complexity and processing requirements increase
Solution Approach 1:
The patent segments the LDPC decoding process into distinct phases (initialization, belief propagation iterations, termination criteria checking) and structures the controller with separate functional units for different decoding operations, making the complex process more manageable and implementable
Solution Approach 2:
The patent implements dynamic decoding by allowing the number of belief propagation iterations to be adjusted based on channel conditions and error rates, and by using adaptive termination criteria that stop decoding when sufficient reliability is achieved, optimizing the balance between complexity and performance
3Productivity
If manual optimization of bit-flipping rules is performed, then decoding performance can be improved, but time consumption and development effort increase
Solution Approach 1:
The patent enables self-service optimization by implementing automated algorithms that generate and optimize bit-flipping rules based on training data and performance metrics, allowing the system to automatically improve its own decoding performance without requiring extensive manual intervention or expert tuning
Solution Approach 2:
The patent incorporates feedback mechanisms where decoding performance is continuously monitored and used to adjust and optimize bit-flipping rules, creating a closed-loop system that automatically improves performance over time based on actual operating conditions and error patterns
Data Source
AI summary
An apparatus of a semiconductor memory system and an operating method thereof include: a plurality of memory devices; and a controller coupled with the memory devices, the controller including a training data storage, a classifier trainer, and a decoder, is configured to perform decoding iterations, wherein the training data storage configured to collect and store at least training data, the classifier trainer configured to train classifiers at least with the training data, and the decoder configured to decode code-bits in accordance with rules of the classifier.