LDPC Decoder Block Processing for Lower Memory and Interconnect Load
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Solution Overview
Problem
Low density parity check (LDPC) decoders face complexity in interconnect issues and require significant computational resources, limiting their efficiency in error correction for next-generation communication and data storage systems.
Innovation Solution
The development of novel techniques for decoding LDPC codes, including the use of check node units (CNUs) with comparators to determine minimum values and a method for processing LDPC codes using log-likelihood ratios, which reduces message storage memory and routing logic, and employs cyclic shifts and parallel processing to simplify the decoding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LDPC decoder designs are used, then error correction capability is achieved, but device complexity and interconnect issues increase
Solution Approach 1:
The decoder is divided into multiple independent check node unit arrays, where each array processes a specific block row of the parity check matrix. This segmentation reduces interconnect complexity by localizing processing functions and minimizing communication requirements between units.
Solution Approach 2:
The patent processes the parity check matrix in a block-by-block row manner, adding a dimensional aspect to the decoding process. This approach transforms the traditional flat processing structure into a multi-dimensional block processing architecture, reducing interconnect requirements.
2Measurement precision
If more computational resources are allocated to LDPC decoding, then decoding accuracy improves, but power consumption and hardware resource utilization increase
Solution Approach 1:
The patent applies partial action by processing the parity check matrix in blocks rather than all-at-once, allowing the decoder to achieve sufficient accuracy with reduced computational resources at any given moment. This block-based approach balances decoding accuracy with power consumption by activating only necessary computational units.
Solution Approach 2:
The invention changes the processing parameter from traditional bit-by-bit or row-by-row decoding to block-based row processing. This parameter change enables more efficient resource utilization and power management while maintaining decoding accuracy through the structured block processing approach.
3Device complexity
If message storage memory is reduced, then hardware resource utilization improves, but decoding capability may be compromised
Solution Approach 1:
By segmenting the processing into block rows and using dedicated check node unit arrays for each block, the patent reduces the amount of message storage memory needed. Each array only needs to store and process its assigned block row data, significantly reducing overall memory requirements while maintaining full decoding capability.
Solution Approach 2:
The patent performs preliminary processing by organizing the parity check matrix into blocks and pre-assigning processing tasks to specific check node unit arrays. This preliminary organization enables efficient memory usage by ensuring that only necessary data is stored and processed at each stage, preventing unnecessary memory consumption.
Data Source
AI summary
A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.