LDPC Decoder Buffer Reuse via First-Pass Syndrome Checking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional error correction decoders require multiple buffers for decoding operations, which increases their size and complexity, particularly due to the need for updating variable nodes in each iteration of the decoding process.

Innovation Solution

An error correction decoder design that refrains from updating variable nodes in the first iteration, using a parity check matrix and sign bits for syndrome checking, and optimizes buffer usage by storing initial soft values in a single buffer, allowing for reduced buffer requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If variable nodes are updated in each iteration of the decoding process, then error correction capability is improved, but the number of buffers required increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidnumber of buffers
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent performs syndrome checking using the parity check matrix and sign bits before updating variable nodes in the first iteration. This preliminary action allows the system to check for errors without requiring additional buffers for storing updated variable node values, thereby reducing buffer requirements while maintaining error correction capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent refrains from updating variable node values in the first iteration, effectively discarding the update step temporarily. This allows the system to perform syndrome checking with the initial soft values from the buffer, then recover and perform updates in subsequent iterations when buffer resources are available or reused

Inventive Principle:
Principle #34Discarding and recovering

2Productivity

If multiple buffers are used for decoding operations, then decoding performance is improved, but device complexity increases

Engineering Contradiction:
Improvedecoding performanceVSAvoiddecoder complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent makes the single buffer serve multiple functions: storing initial soft values for syndrome checking, and subsequently storing updated variable node values in later iterations. This multi-functionality reduces the total number of buffers needed while maintaining decoding performance across multiple iterations

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the functions of multiple buffers into a single buffer by temporal multiplexing - the same buffer is used for different purposes at different times (first for syndrome checking, then for storing updated values), thereby reducing device complexity while preserving decoding capabilities

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If variable node updates are performed in every iteration, then error correction accuracy is improved, but buffer memory requirements increase

Engineering Contradiction:
Improveerror correction accuracyVSAvoidbuffer memory size
Core Design Contradiction:
Measurement precisionVSVolume of stationary object

Solution Approach 1:

The patent implements periodic variable node updates rather than continuous updates in every iteration. By performing syndrome checking without updates in the first iteration and then updating in subsequent iterations, the system maintains error correction accuracy over time while reducing peak buffer memory requirements

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11128315B2Error correction decoder
Publication Date: 2021.09.21 MIMIRIP LLC
  • US11128315B2 patent drawing
  • US11128315B2 patent drawing
  • US11128315B2 patent drawing

AI summary

Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.