LDPC Decoder Check-Node Counting for Lower Complexity
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Solution Overview
Problem
In flash memory systems using low density parity check (LDPC) codes, existing decoders face challenges in maintaining error correction performance while minimizing computational complexity, particularly in counting the number of messages with specific reliability and determining the magnitude of check-to-variable messages efficiently.
Innovation Solution
The method involves a decoder architecture with variable nodes and check nodes that receive variable-to-check messages, count messages of specific magnitude, and determine the magnitude of check-to-variable messages based on count values and message magnitudes, thereby reducing computational complexity and enhancing error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the min-sum algorithm is used to calculate the magnitude of C2V messages in LDPC decoders, then error correction performance is maintained, but computational complexity increases due to the need to count messages with specific reliability and determine message magnitudes
Solution Approach 1:
The check node is divided into multiple sub-check nodes, each responsible for counting messages with specific magnitudes. This segmentation allows the complex counting operation to be distributed across multiple simpler units, reducing the computational burden on any single node while maintaining the overall error correction performance of the min-sum algorithm.
Solution Approach 2:
The patent pre-calculates and stores magnitude information for V2C messages before they are processed in the min-sum algorithm. By preparing magnitude data in advance, the decoder avoids performing complex real-time calculations during the main decoding process, thereby reducing computational complexity while preserving error correction capability.
2Measurement precision
If counters with more output bits are used to accurately count messages of specific magnitude, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
Different sub-check nodes use counters with different numbers of output bits based on their specific counting requirements. Rather than uniformly using high-precision counters throughout the system, the patent applies appropriate precision locally to each sub-check node, reducing overall device complexity and power consumption while maintaining sufficient measurement precision for error correction.
Solution Approach 2:
The patent dynamically adjusts the number of output bits in counters based on the magnitude range and distribution of messages being counted. By adapting counter precision to the actual data characteristics, the system achieves accurate message counting without the overhead of always using maximum-precision counters, thereby reducing complexity and power consumption.
3Device complexity
If the number of output bits in counters is reduced to decrease device complexity, then computational complexity is reduced, but measurement precision of message counting deteriorates
Solution Approach 1:
The counting function is segmented across multiple sub-check nodes, each handling a specific magnitude range with appropriately sized counters. This segmentation allows the use of smaller counters (fewer output bits) in each node while collectively achieving accurate overall message counting, thus reducing device complexity without sacrificing measurement precision.
Solution Approach 2:
Each sub-check node performs a partial counting function focusing on specific message magnitudes rather than counting all messages. By dividing the counting task into multiple partial operations, the system achieves complete and accurate message counting using smaller, lower-complexity counters, thereby reducing device complexity while maintaining precision.
Data Source
AI summary
A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.