Multi-Standard LDPC Decoder With Circular Shifting for Higher Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional LDPC decoders require significant silicon area and inefficiencies due to the need for multiple processors and RAM access contentions when processing various wireless communication standards, limiting throughput and increasing hardware requirements.
Innovation Solution
A multi-standard LDPC decoder architecture that reuses data paths, RAM, and logic circuits to process multiple smaller code words simultaneously, using a circular shifter to address unused data paths and reduce RAM access contentions by allowing read and write operations in the same cycle, and storing extra rows of CNU results to enable flexible VNU operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple separate LDPC decoders are used to support different wireless communication standards, then each standard can be processed correctly, but the silicon area consumed increases significantly
Solution Approach 1:
The patent implements a universal LDPC decoder architecture that can process multiple wireless communication standards (5G NR, Wi-Fi 6, etc.) using a single hardware structure. The decoder uses configurable parameters such as code block size, number of rows and columns, and iteration counts to adapt to different standards without requiring separate dedicated decoders for each standard, thereby reducing silicon area while maintaining multi-standard support capability
Solution Approach 2:
The decoder employs dynamic configuration where processing parameters (code block size, matrix dimensions, iteration numbers) can be adjusted based on the specific standard being processed. This dynamic adaptability allows the same hardware to efficiently handle variable-length code blocks and different parity check matrix sizes according to the requirements of different wireless communication standards
2Productivity
If multiple parallel CNU and VNU processors are used to increase throughput, then system throughput requirements are met, but data dependency and RAM access collisions increase
Solution Approach 1:
The patent segments the processing into distinct stages: check node updating (CNU) processors process parity check matrix rows independently, store results in intermediate memory, and then variable node updating (VNU) processors process the results. This segmentation allows parallel processing while managing data dependencies through structured memory interfaces, reducing access collisions by organizing data flow in discrete processing stages
Solution Approach 2:
The patent introduces intermediate memory structures and control logic that mediate between CNU and VNU processors. These intermediaries buffer data between processing stages, manage timing and data flow, and coordinate RAM access patterns to minimize collisions while maintaining high throughput through efficient parallel processing
3Quantity of substance
If more CNU and VNU processors are added to process larger matrices, then larger code blocks can be processed, but the number of silicon-consuming processors increases
Solution Approach 1:
The patent implements a hierarchical processing structure where smaller processing units (CNU and VNU processors) are nested within a larger unified decoder framework. Multiple processors work on different segments of the parity check matrix simultaneously, with results combined through the intermediate memory structure. This nested architecture enables processing of large code blocks by distributing work across multiple processors while sharing common control and memory resources, reducing the overall silicon area compared to having fully independent processors for each function
Data Source
AI summary
A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.