LDPC Bit-Flipping Decoder With Out-of-Order Column Processing
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Solution Overview
Problem
Existing bit-flipping (BF) decoders in non-volatile memory devices, such as SSDs, face high latency due to inefficiencies in processing circulant columns of LDPC codes, leading to increased power consumption and degraded performance, especially in mobile and client SSD applications with strict power constraints and throughput requirements.
Innovation Solution
Implementing an out-of-order processing method for circulant columns based on a quality metric, using an on-the-fly column quality estimator to sort and selectively process columns, thereby reducing unnecessary processing and calculating cyclic redundancy check (CRC) parity, which speeds up convergence and reduces latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If bit-flipping decoders process circulant columns in traditional order, then decoding can be completed, but latency is high and convergence is slow
Solution Approach 1:
The patent applies dynamics by making the processing order of circulant columns flexible and adaptive rather than fixed. The decoder dynamically determines the processing sequence based on real-time quality metrics of each column, allowing the system to adapt to varying error patterns and optimize convergence speed for different decoding scenarios.
Solution Approach 2:
The patent changes the parameter of processing order from a fixed sequence to a variable sequence determined by quality metrics. By evaluating and reordering columns based on their error characteristics, the system transforms a static decoding process into one that dynamically adjusts parameters to optimize performance.
2Reliability
If all circulant columns are processed in every iteration, then decoding accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent applies partial action by processing only a subset of circulant columns in each iteration rather than all columns. The quality metric evaluation identifies which columns require processing, allowing the system to perform partial decoding operations that maintain reliability while reducing unnecessary energy expenditure on already-corrected columns.
Solution Approach 2:
The patent applies local quality by treating different circulant columns differently based on their individual quality metrics. Instead of uniform processing, the system identifies and focuses computational resources on columns with higher error probabilities, optimizing the trade-off between reliability and power consumption at the local column level.
3Reliability
If strong error-correction codes are used to protect data, then data reliability improves, but storage space increases due to ECC parity bits
Solution Approach 1:
The patent applies segmentation by dividing the error correction process into independent circulant column segments. Each column can be evaluated and processed separately based on its quality metric, allowing efficient utilization of ECC parity bits without requiring excessive redundancy, thus optimizing the balance between reliability and storage space.
Data Source
AI summary
Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.