LDPC Bit-Flip Decoder Column Scheduling for Accurate Pipelining

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Solution Overview

Problem

Conventional bit-flipping LDPC decoders face accuracy degradation due to concurrent processing of parity columns in pipeline and parallel processing, especially when there are high row overlaps between columns.

Innovation Solution

Reordering columns of the parity matrix to separate parity columns, organizing them into cycle blocks and pipeline blocks, and assigning them to processing units to avoid concurrent processing of multiple parity columns, ensuring each processing unit processes only one parity column at a time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If concurrent processing of parity columns is implemented in pipeline and parallel processing, then throughput is enhanced, but accuracy degrades due to outdated syndrome states

Engineering Contradiction:

ImprovethroughputVSAvoiddecoding accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The parity columns are segmented into different processing groups (first plurality and second plurality) that are processed at different times. The first parity columns are processed in an initial cycle, followed by the second parity columns in subsequent cycles, preventing concurrent processing of multiple parity columns while maintaining pipeline efficiency

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The processing is organized into periodic cycles where parity columns are processed sequentially across different cycles rather than concurrently within the same cycle. This periodic scheduling ensures that syndrome states remain current and accurate for each processing stage

Inventive Principle:

Principle #19Periodic action

2Speed

If parity columns are processed in parallel across multiple processing units, then processing speed increases, but accuracy degrades when there are high row overlaps between columns

Engineering Contradiction:

Improveprocessing speedVSAvoiddecoding accuracy

Core Design Contradiction:

SpeedVSMeasurement precision

Solution Approach 1:

Parity columns with high row overlaps are segmented into different processing groups that are not processed simultaneously. The first plurality of parity columns is assigned to one set of processing operations while the second plurality is assigned to subsequent processing operations, eliminating the accuracy degradation caused by concurrent processing of overlapping columns

Inventive Principle:

Principle #1Segmentation

3Productivity

If multiple parity columns are processed concurrently in the same cycle, then productivity improves, but outdated syndrome states cause errors

Engineering Contradiction:

Improveprocessing capacityVSAvoiddecoding reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The syndrome values are updated and made available to subsequent processing stages before the next parity column processing begins. This preliminary updating ensures that when the second plurality of parity columns is processed, the syndrome states are already current and accurate, preventing reliability degradation

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20240338146A1Separation of Parity Columns in Bit-Flip Decoding of Low-Density Parity-Check Codes with Pipelining and Column Parallelism

Publication Date: 2024.10.10 MICRON TECHNOLOGY INC

AI summary

A memory device having a bit-flipping decoder. The decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. The decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.