5G LDPC Decoder Configuration Subset for Satellite Throughput

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Solution Overview

Problem

Conventional 5G LDPC decoders face high hardware implementation complexity and inefficiency due to their ultra-flexibility, which is not suitable for space-related constraints such as size, weight, and energy consumption, and their parallel architecture is suboptimal for low expansion factor values.

Innovation Solution

An LDPC decoder that selects a limited number of predefined configurations from the 5G LDPC configurations, precalculates and stores their parity matrices, optimizing hardware resources and reducing complexity by using a multi-core approach with shared memory and optimized scheduling of parity check nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional 5G LDPC decoders support all 5G LDPC configurations with ultra-flexibility, then adaptability to different transmission conditions is improved, but hardware implementation complexity increases

Engineering Contradiction:
Improveadaptability to different transmission conditionsVSAvoidhardware implementation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The decoder is divided into multiple independent cores, each capable of handling specific LDPC configurations. This segmentation allows the system to support multiple configurations without requiring a single complex decoder to handle all cases, thereby reducing overall hardware complexity while maintaining adaptability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each decoder core is designed with universal functionality to handle various LDPC configurations through configurable parameters. The cores can be dynamically configured to support different code rates, block lengths, and expansion factors, providing multi-functionality without requiring separate dedicated hardware for each configuration.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If conventional 5G LDPC decoders use parallel architecture to improve throughput, then productivity is improved, but device complexity increases for low expansion factor values

Engineering Contradiction:
ImprovethroughputVSAvoiddevice complexity for low expansion factor
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The parallel architecture is made dynamic by allowing the number of active cores and their configuration to be adjusted based on the expansion factor value. For low expansion factors, fewer cores are activated or cores are configured with appropriate parallelism levels, reducing complexity while maintaining throughput efficiency. For high expansion factors, more cores are activated to maximize throughput.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If 5G LDPC codes support a very large number of configurations to improve adaptability, then adaptability is improved, but memory requirements increase

Engineering Contradiction:
Improvenumber of supported configurationsVSAvoidmemory requirements
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

Multiple LDPC configuration parameters (parity matrix, permutation matrices, check node degrees) are merged into a unified configuration data structure stored in memory. This consolidation reduces redundant storage and optimizes memory usage while supporting a large number of configurations. The configuration data is organized to be efficiently loaded and applied across multiple decoder cores.

Inventive Principle:
Principle #5Merging (Combining)

4Productivity

If conventional 5G LDPC decoders use high parallelism to improve throughput, then productivity is improved, but power consumption increases

Engineering Contradiction:
ImprovethroughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

Instead of activating all decoder cores at full parallelism for every operation, the system applies partial action by dynamically activating only the necessary number of cores based on the specific configuration requirements and throughput demands. This reduces power consumption by keeping unnecessary cores in low-power states while maintaining adequate throughput performance.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP4595232B15g compatible LDPC decoder for satellite communications
Publication Date: 2025.10.01 AIRBUS DEFENCE & SPACE SAS
  • EP4595232B1 patent drawingFigure 1~2
  • EP4595232B1 patent drawingFigure 3
  • EP4595232B1 patent drawingFigure 4~5

AI summary

The invention relates to a decoder (30) for decoding low-density parity-check (LDPC) codewords. The decoder includes at least one core (10) and a memory (20) in which a number NC of predefined configurations is stored. The core is suitable for being dynamically configured with any one of the NC predefined configurations stored in the memory in order to decode an LDPC codeword using this configuration. The NC predefined configurations form a sub-group, in the strict sense, of 5G LDPC configurations defined in the 3GPP TS 38.212 standard. Each configuration corresponds to a triplet of three parameters {K, R, Z}, and to a parity matrix constructed according to at least a portion of these parameters. K is a message size encoded by the LDPC code, Z is an expansion factor of the parity matrix, and R is a code rate of the LDPC code. Advantageously, the NC predefined configurations include different values of the parameter Z.