Parallel LDPC Decoder with Convergence Checking for Low-Power Throughput
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Solution Overview
Problem
Current data storage devices face challenges in achieving high decoder performance for LDPC codes without increasing complexity or power consumption, which affects data rate and system efficiency.
Innovation Solution
A high-performance decoder circuit is designed with a check node processor that provides parallel c2v message vectors to a variable node processor, along with a convergence checker to determine decoding convergence, optimizing the decoding process for low complexity and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel processing is implemented to improve decoder performance, then productivity increases, but device complexity increases
Solution Approach 1:
The decoder is segmented into specialized functional units: check node processors that operate in parallel to compute check-to-variable messages, variable node processors that compute variable-to-check messages, and a convergence checker. This segmentation enables parallel processing while managing complexity through functional decomposition.
Solution Approach 2:
The patent transitions from sequential bit-by-bit decoding to parallel vector-based processing, adding a dimension of parallelism. Multiple check node processors simultaneously process different portions of the codeword, and multiple variable node processors simultaneously update their states, dramatically improving throughput.
2Productivity
If more processing units are added to improve decoding speed, then productivity increases, but power consumption increases
Solution Approach 1:
The decoder employs iterative periodic action where check node processors and variable node processors alternate in computing messages. The convergence checker periodically evaluates whether decoding has converged, allowing the system to terminate early when successful rather than completing a fixed number of iterations, thus reducing average power consumption.
Solution Approach 2:
The convergence checker provides feedback to determine when decoding is complete. This feedback mechanism allows the parallel processing units to operate only as long as necessary, dynamically adjusting total power consumption based on the actual decoding requirements rather than operating at maximum capacity continuously.
Data Source
AI summary
Systems and methods are disclosed for implementing a high performance decoder. In certain embodiments, an apparatus may comprise a decoder circuit configured to decode a codeword of bits, including: a check node processor configured to provide a plurality of check to variable (c2v) messages to a variable node processor in parallel, the plurality of c2v messages including log likelihood ratio (LLR) data related a parity sum of multiple bits of the codeword; the variable node processor configured to generate a decision vector based on the plurality of c2v messages; and a convergence checker circuit configured to determine whether the codeword has been decoded based on the decision vector and output decoded data when the codeword has been decoded.