LDPC Min-Sum Decoder Correction for Low-Power Iterative Decoding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Iterative error correcting decoders, such as LDPC decoders, face a trade-off between the number of iterations and power complexity, with higher iterations improving bit error rate but increasing power consumption, and existing min-sum algorithms suffer from lower decoding gain and higher logic complexity.

Innovation Solution

Implementing a min-sum with correction algorithm that reduces message resolution and logic complexity by using a correction factor, such as p·2q, to bring performance closer to sum-product algorithms without compromising performance, specifically by adjusting the parity check node outputs based on input magnitudes and thresholds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of iterations is increased to improve bit error rate, then decoding performance is improved, but power consumption increases

Engineering Contradiction:
Improvebit error rateVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the parameter of message resolution from high precision to reduced precision (e.g., from multiple bits to single bit or fewer bits) while maintaining decoding performance. This parameter change allows the decoder to achieve the same bit error rate with fewer computational operations, thereby reducing power consumption without sacrificing reliability

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If min-sum algorithm is used to reduce power complexity, then power consumption is reduced, but decoding gain decreases

Engineering Contradiction:
Improvepower complexityVSAvoiddecoding gain
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent modifies the min-sum algorithm by changing the parameter of message representation to reduced resolution (lower precision). This parameter change enables the algorithm to maintain decoding gain comparable to sum-product algorithms while keeping power complexity low, as the reduced precision simplifies the computational operations without fundamentally compromising the decoding accuracy

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If message resolution is reduced to lower logic complexity, then device complexity is reduced, but decoding performance may be compromised

Engineering Contradiction:
Improvelogic complexityVSAvoiddecoding performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent changes the parameter of message resolution to a reduced value (lower precision) and demonstrates that this parameter change does not compromise decoding performance when used with the modified min-sum algorithm. The reduced resolution simplifies the logic complexity by requiring fewer bits for message representation and simpler computational operations, while the algorithm modification ensures that decoding performance is maintained

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8281210B1Optimized correction factor for low-power min-sum low density parity check decoder (LDPC)
Publication Date: 2012.10.02 MARVELL ASIA PTE LTD
  • US8281210B1 patent drawing
  • US8281210B1 patent drawing
  • US8281210B1 patent drawing

AI summary

An iterative decoder configured to implement a min-sum with correction algorithm. The iterative decoder includes N parity check nodes coupled to M equality constraint nodes. The iterative decoder further includes a first parity check node configured to send an output to a first equality constraint node. Responsive to a minimum magnitude of other M−1 inputs to the first parity check node being lower than a pre-determined threshold, the parity check node sends the output having a same magnitude as that of the minimum magnitude of the other M−1 inputs to the first parity check node. Responsive to the minimum magnitude of the other M−1 inputs to the first parity check node being greater than the pre-determined threshold, the parity check node subtracts a correction factor in the form of p·2q from the minimum magnitude.