LDPC Decoder Parallel Architecture With Router-Free Cyclic Shifts
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Solution Overview
Problem
Existing low density parity check (LDPC) decoders face challenges in reducing message storage memory and message routing logic, particularly in parallel implementations, which can lead to complex interconnect issues.
Innovation Solution
The proposed LDPC decoder employs a check node unit (CNU) with a set of comparators that compare stored minimum values to a received variable message, reducing the number of comparators needed and optimizing message processing. Additionally, the decoder incorporates a method for cyclic shift processing without active routers, simplifying interconnects and enhancing parallelization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a parallel LDPC decoder implementation is used, then decoding speed and productivity are improved, but device complexity and interconnect issues worsen
Solution Approach 1:
The decoder is divided into multiple check node units (CNUs), each processing a specific subset of parity check equations. This segmentation allows parallel processing of different code blocks simultaneously, improving decoding speed while keeping each CNU's internal logic relatively simple and manageable
Solution Approach 2:
The patent introduces a hierarchical processing structure where CNUs process data in stages (first stage, second stage, third stage). This multi-dimensional processing approach allows the system to achieve high parallelism through time-staged processing rather than requiring all processors to operate simultaneously with complex interconnects
2Measurement precision
If the number of comparators in each CNU is increased, then measurement precision and minimum value determination accuracy are improved, but device complexity increases
Solution Approach 1:
Each CNU uses a limited set of comparators (first comparator, second comparator, third comparator) to determine the two minimum values needed for decoding. Rather than using an exhaustive number of comparators to check all possible values, the patent applies partial action by strategically comparing only the necessary minimum values, achieving sufficient precision with reduced complexity
Solution Approach 2:
The patent performs preliminary sorting and selection of minimum values within each CNU before passing results to the next processing stage. This preliminary action ensures that only the essential minimum values are transmitted forward, maintaining accuracy while reducing the complexity of subsequent processing stages
3Adaptability or versatility
If active routers are used for cyclic shift processing, then message routing flexibility is improved, but device complexity and interconnect issues worsen
Solution Approach 1:
Instead of using complex active routers to dynamically route messages, the patent uses predetermined routing patterns based on the structured LDPC code properties. The routing behavior is essentially copied from the known code structure, eliminating the need for complex decision-making logic in routers while maintaining correct message flow
Solution Approach 2:
Rather than using active routers to dynamically determine message paths, the patent inverts the approach by using the structured properties of the LDPC code to predeterminedly establish routing patterns. This inversion replaces complex active routing logic with simpler, structure-based routing that achieves the same flexibility through code design rather than hardware complexity
Data Source
AI summary
A method and system for decoding low density parity check (LDPC) codes. A method includes performing block parallel processing that initiates processing all non-zero block columns of a plurality (M) of rows of a layer of an LDPC matrix in each clock cycle, where M≤p, and p is a total number of rows in a layer of the LDPC matrix; and updating a P message responsive to determination of a final state for each row of the LDPC matrix. The LDPC matrix includes layers, each comprising a plurality (M) of rows that are processed per clock cycle. Each of the plurality of rows of each of the layers is datawise independent of the rows processed during a previous NP_MAX clock cycles and at least one row in each layer is datawise dependent on a row of an immediately preceding layer, and NP_MAX is greater than one.