LDPC Decoder Daisy-Chain Layout for High-Throughput Message Passing
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Solution Overview
Problem
Existing LDPC decoding systems face challenges in managing large memory requirements and hardware complexity due to the need to store and process numerous bit and check edge messages, which limits their efficiency and throughput in high-data-rate communication systems.
Innovation Solution
The implementation of a distributed processing technique using a daisy chain architecture with localized MUXs and registers, which allows for efficient message passing and processing by exploiting the sub-matrix structure of the low density parity check matrix, reducing memory needs and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LDPC decoding systems store and process all bit and check edge messages using large memory structures, then decoding accuracy is maintained, but memory storage requirements and hardware complexity increase significantly
Solution Approach 1:
The patent divides the LDPC code into multiple sub-matrices and processes each sub-matrix separately using distributed processing elements. This segmentation allows the system to maintain decoding accuracy by processing all necessary messages while distributing the computational load across multiple smaller processing units rather than requiring one large memory structure, thereby reducing overall hardware complexity and memory requirements.
Solution Approach 2:
The patent introduces a spatial dimension to the processing architecture by arranging processing elements in a two-dimensional array that corresponds to the sub-matrix structure. This dimensional organization allows messages to be processed in a distributed manner across the array, reducing the need for large centralized memory while maintaining all necessary data for accurate decoding through localized message passing between adjacent processing elements.
2Ease of operation
If traditional LDPC decoding systems use centralized memory structures to manage all edge messages, then message management is simplified, but routing congestion and processing delays increase
Solution Approach 1:
The patent segments the centralized memory structure into multiple distributed processing elements, each handling a specific sub-matrix. This segmentation distributes the message management workload across multiple units, reducing routing congestion and processing delays while maintaining organized message flow through localized exchanges between processing elements that correspond to the sub-matrix structure.
Solution Approach 2:
The patent implements local message passing between adjacent processing elements in the distributed array, where each element only communicates with its neighbors corresponding to connected nodes in the LDPC graph. This local quality approach reduces overall routing congestion by eliminating long-distance message transfers while maintaining proper message management through structured local exchanges.
3Productivity
If LDPC decoders are designed for high data rate communication systems, then throughput requirements increase, but memory access conflicts and processing bottlenecks worsen
Solution Approach 1:
The patent segments the processing function into multiple parallel processing elements that can simultaneously process different sub-matrices. This segmentation enables the system to achieve high data throughput by parallelizing the decoding process while reducing memory access conflicts, as each processing element has its own localized memory and only accesses messages relevant to its specific sub-matrix processing.
Data Source
AI summary
Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices).