Layered LDPC Decoder Pipeline With Dual-Bank LLR Memory
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Solution Overview
Problem
Current wireless communication systems face challenges in efficiently decoding low-density parity-check (LDPC) codes, particularly in high-throughput applications, due to processing delays and memory conflicts arising from the dependency between bit log-likelihood ratios (LLRs) and a posteriori LLRs in layered LDPC decoders.
Innovation Solution
The proposed solution involves a deeply-pipelined layered LDPC decoder architecture that relaxes the dependency between updating bit LLRs and computing a posteriori LLRs, allowing the use of outdated LLRs for initial a posteriori processing, and utilizing updated LLRs as they become available, while also addressing memory conflicts through dual bank memory organization to enhance processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a deeply-pipelined layered LDPC decoder architecture is implemented to increase processing throughput, then productivity is improved, but device complexity increases due to dual bank memory organization and relaxed dependency handling
Solution Approach 1:
The decoder is divided into multiple pipeline stages with dual bank memory structures. Each stage processes specific portions of the decoding computation independently, allowing parallel processing of different code blocks and increasing overall throughput while managing complexity through modular organization.
Solution Approach 2:
The patent introduces a time dimension to the memory organization by implementing dual bank memories that operate in alternating phases. This temporal dimension allows the system to overcome the dependency between bit LLRs and a posteriori LLRs by storing outdated LLRs in one bank while computing with updated values in the other, effectively decoupling the computational stages.
2Speed
If the dependency between updating bit LLRs and computing a posteriori LLRs is relaxed to enable deeper pipelining, then processing speed is improved, but measurement precision deteriorates due to use of outdated LLRs
Solution Approach 1:
The dual bank memory structure prepares outdated LLRs in advance in one bank while the other bank is being used for current computations. This preliminary storage of historical LLR values allows the pipeline to proceed without waiting for updates, maintaining processing speed while preserving the ability to use accurate updated values when available.
Solution Approach 2:
The dual bank memory acts as an intermediary between the LLR update process and the a posteriori computation process. It buffers the transition from outdated to updated LLRs, allowing computations to proceed with available data while ensuring that updated values are properly integrated when ready, thus maintaining both speed and precision.
3Productivity
If dual bank memory organization is implemented to resolve memory conflicts, then productivity is improved, but device complexity increases due to additional memory infrastructure
Solution Approach 1:
The memory system is segmented into two separate banks that handle different phases of the decoding process. This segmentation eliminates memory conflicts by ensuring that read and write operations occur in different banks simultaneously, doubling the effective memory bandwidth available to the decoder while organizing complexity into manageable independent units.
Solution Approach 2:
The dual bank memory operates in a periodic alternating fashion, with one bank active for reads while the other performs writes, then switching in the next phase. This periodic operation pattern maximizes memory utilization and throughput while keeping the control logic relatively simple through regular, predictable switching behavior.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs. Accordingly, aspects of the present disclosure provide techniques for reducing delays in a processing pipeline by, in some cases, relaxing a dependency between updating bit log likelihood ratios (LLRs) and computing a posteriori LLRs.