LDPC Decoder Architecture With Dynamic I/O for Lower Latency
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Solution Overview
Problem
Conventional LDPC decoder implementations for 3GPP New Radio LDPC codes require significant hardware resources and result in high latency due to the need for numerous rotators, core variable node memories, and check node processors, as well as a large number of decoding operations, leading to inefficient throughput.
Innovation Solution
The proposed solution involves an LDPC decoder architecture with two or more check node sub-processors, each with multiple input/output ports, and a controller that activates subsets of I/O ports based on the decoding operation, allowing for reduced hardware requirements and fewer decoding operations by processing multiple rows concurrently and optimizing the use of rotators and memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional LDPC decoder implementations use multiple rotators, core variable node memories, and check node processors to process multiple rows concurrently, then processing capability is improved, but hardware resources and device complexity increase significantly
Solution Approach 1:
The check node processor is divided into multiple check node sub-processors, each handling specific rows of the parity check matrix. This segmentation allows parallel processing of multiple rows while using fewer total resources than a monolithic processor, as each sub-processor is specialized for a subset of operations.
Solution Approach 2:
The check node sub-processors are designed to be multi-functional, capable of processing different types of rows (e.g., core rows and extension rows) by configuring their I/O ports dynamically. This universality reduces the need for dedicated hardware for each row type, optimizing resource utilization.
2Reliability
If conventional LDPC decoder implementations activate all I/O ports of check node processors for each decoding operation, then processing completeness is ensured, but the number of decoding operations and latency increase
Solution Approach 1:
The controller dynamically activates only the necessary subset of I/O ports for each decoding operation based on the specific row being processed and the current decoding state. This dynamic configuration reduces the number of active ports per operation, decreasing processing overhead and latency while maintaining complete processing of all required rows across multiple operations.
Data Source
AI summary
An electronic device, configured to perform a series of low-density parity check, LDPC, decoding operations for a parity check matrix, PCM, derived from at least one basegraph having a plurality of rows, includes: two or more check node, CN, sub-processors having input-output (I-O) port(s); and a controller configured to activate a subset of the I-O port(s) based on a current LDPC decoding sub-step of the LDPC decoding operations and the basegraph. The CN sub-processors support: a first single LDPC decoding operation to perform LDPC decoding computations for two or more rows of the PCM that are derived from different orthogonal rows of the plurality of rows in the basegraph; and a second mode whereby two or more of CN sub-processors co-operate to perform LDPC decoding computations for two or more rows of the PCM that are derived from a single row in the basegraph.