LDPC Decoder Memory Layout for Simultaneous Edge Access

The patent divides the memory access architecture into multiple independent memory modules (first memory module, second memory module, third memory module, fourth memory module) that can be accessed simultaneously by different processing nodes. This segmentation allows variable nodes and check nodes to perform operations in parallel without conflicting for the same memory resource, thereby increasing decoding speed while maintaining manageable device complexity through modular design.

The patent introduces a new dimension of parallelism by implementing simultaneous read and write operations in different memory modules during the same processing cycle. Instead of sequential access in a single dimension, the system enables multi-dimensional concurrent access where variable nodes read from one memory module while check nodes write to another, effectively utilizing multiple memory dimensions to achieve higher processing throughput.

The memory system is segmented into four distinct memory modules, each handling specific types of data access. This segmentation allows different processing nodes to operate independently on different memory modules simultaneously, achieving high productivity without requiring complex arbitration logic for shared memory access, as each module operates as an independent resource.

The patent introduces buffer memory structures that act as intermediaries between processing nodes and the memory modules. These buffers manage the data flow and coordination between simultaneous read and write operations, simplifying the control complexity by providing a standardized interface layer that handles the coordination of parallel accesses without requiring complex direct control logic.

The patent segments the memory access structure into multiple parallel pathways with dedicated memory modules for different operations. This segmentation eliminates sequential bottlenecks by allowing variable node updates and check node computations to occur simultaneously in different memory modules, significantly reducing total decoding time while maintaining a structured and organized memory architecture.

The patent implements preliminary organization of memory modules where data is pre-positioned in appropriate memory locations based on the processing requirements. Variable node data, check node data, and syndrome data are stored in dedicated memory modules before processing begins, allowing immediate parallel access without sequential data retrieval delays, thus reducing processing time while keeping the memory structure systematic.