LDPC Decoder Neural Segmentation for NAND Flash Error Floors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash-based storage devices face challenges with data reliability and error correction due to increased noise and interference at smaller fabrication sizes, requiring more powerful error correction codes like LDPC, but traditional decoding methods struggle with error floors, especially in parity regions.
Innovation Solution
A memory system with a bit-flipping (BF) LDPC decoder that employs a trained neural network assembly and data separation component to handle variable nodes of different degrees, using multiple training neural networks to reduce errors by clustering and optimizing weights based on degree distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional decoding methods are used in LDPC decoders, then device complexity is reduced, but error correction performance deteriorates due to error floors in parity regions
Solution Approach 1:
The decoder is segmented into multiple specialized components: a trained neural network assembly for initial decoding, a data separation component that divides unsuccessfully decoded data by variable node degree, and multiple training neural networks (first through fourth) that specialize in correcting errors for different variable node degree clusters. This segmentation allows each component to optimize for specific error patterns, reducing the overall error floor while distributing complexity across modular units.
Solution Approach 2:
Different neural networks are trained with different weights optimized for specific local characteristics of variable nodes. The first and second training neural networks handle variable nodes with degrees in a first cluster, while the third and fourth training neural networks handle variable nodes with degrees in a second cluster. This local quality approach ensures that each neural network is specially optimized for its designated subset of variable nodes, improving overall error correction performance.
2Reliability
If multiple training neural networks are used to reduce error floors, then data reliability improves, but device complexity increases
Solution Approach 1:
The neural networks are trained in advance using training data that includes successfully decoded data and unsuccessfully decoded data separated by variable node degree. The training process pre-optimizes the weights of each neural network for its specific cluster of variable nodes before actual decoding operations. This preliminary action ensures that when the decoder operates, the neural networks are already optimized and ready to handle their specific error patterns, improving reliability without requiring complex real-time adjustments.
Solution Approach 2:
The system changes parameters by using different weight configurations for different neural networks based on variable node degree clusters. The first and second training neural networks have weights optimized for variable nodes with degrees in a first cluster, while the third and fourth training neural networks have weights optimized for variable nodes with degrees in a second cluster. This parameter change approach allows the system to adapt to different error patterns associated with different variable node degrees, improving data integrity while managing complexity through parameter specialization rather than structural complexity.
3Measurement precision
If variable nodes are processed uniformly without degree-based separation, then device complexity is minimized, but measurement precision of error patterns deteriorates
Solution Approach 1:
The data separation component segments unsuccessfully decoded data into different groups based on the degree of variable nodes. Variable nodes are clustered into different degree groups, and each cluster is processed by specialized neural networks. This segmentation enables precise error pattern recognition for each variable node degree cluster, as each neural network can be trained to recognize the specific error patterns characteristic of its designated cluster, rather than attempting to handle all variable nodes uniformly.
Data Source
AI summary
A memory system, a bit-flipping (BF) low-density parity check (LDPC) decoder included in the memory system and operating methods thereof in which such decoder or decoding has a reduced error floor. Such a BF LDPC decoder is configured using a deep learning framework of trained and training neural networks and data separation that exploits the degree distribution information of the constructed LDPC codes.