LDPC Decoder Error Path Resetting for Flash Memory Read Failures
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Solution Overview
Problem
In semiconductor memory devices, particularly in multi-level cell (MLC) and triple-level cell (TLC) flash memory, the increasing number of bits programmed per cell leads to reliability issues and read failure due to overlapping threshold voltage distributions, resulting in significant error rates during data retrieval.
Innovation Solution
A semiconductor memory system incorporating a low-density parity check (LDPC) decoder that performs message passing decoding and error path detection to correct errors by resetting symbol values and log likelihood ratios (LLRs) in error path candidates, thereby improving decoding performance in the error floor region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits programmed in each memory cell increases (MLC, TLC), then data storage capacity and integration density are improved, but reliability decreases and read failure rate increases due to overlapping threshold voltage distributions
Solution Approach 1:
The patent segments the error correction process into multiple stages: initial LDPC decoding, identification of unsatisfied check nodes (UCNs), error path detection using tree structures, and targeted LLR resetting. This segmentation allows the system to handle errors systematically rather than attempting uniform correction, improving reliability without sacrificing storage capacity.
Solution Approach 2:
The patent introduces an intermediary error path detection mechanism that acts as a mediator between the initial decoding failure and final error correction. By detecting error paths through tree structures and identifying UCNs, the system creates an intermediate analysis layer that guides targeted LLR resetting, bridging the gap between failed decoding and successful error correction.
2Device complexity
If conventional LDPC decoding is used without error path detection, then device complexity is low, but decoding performance deteriorates in error floor region
Solution Approach 1:
The patent performs preliminary actions by detecting error paths and identifying unsatisfied check nodes before attempting final error correction. The tree-based error path detection and UCN identification are executed in advance to guide the LLR resetting process, ensuring that correction efforts are focused on the most likely error sources rather than applying uniform correction.
Solution Approach 2:
The patent introduces dynamic adaptability into the decoding process by conditionally resetting LLRs based on detected error paths and UCNs. Rather than applying static correction methods, the system dynamically adjusts its correction strategy based on the specific error patterns identified during decoding, allowing optimal performance across varying error conditions.
Data Source
AI summary
A semiconductor memory system including: a semiconductor memory device suitable for storing a codeword; and an LDPC decoder suitable for decoding the codeword to generate decoded data, wherein the LDPC decoder includes: a message passing decoding component suitable for performing a first decoding operation of decoding the codeword, and calculating the minimum value among numbers of UCNs; and an error path detection component suitable for detecting error path candidates using a tree in which each of UCNs corresponding to the minimum value is set to a root node, sorting the detected error path candidates in ascending order of maximum LLRs, resetting symbol values and LLRs of variable nodes in the error path candidates, and providing the message passing decoding unit with information on the reset symbol values and LLRs.