LDPC Decoder Pipeline With Fixed Permutation and Shift Registers
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Solution Overview
Problem
Low-density parity-check (LDPC) decoding is computationally complex, leading to increased memory requirements and interconnection complexity, which hinders efficient processing in systems like 60 GHz millimeter wave systems.
Innovation Solution
An iterative LDPC decoding system comprising shift-registers for bit estimates, parity-check processing units, combining means for updating bit estimates, and fixed permutation mechanisms to simplify storage and access, along with a pipelined configuration for multi-rate processing, reduces computational complexity and decoder size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative LDPC decoding algorithms are used to achieve accurate error correction, then decoding reliability is improved, but computational complexity increases
Solution Approach 1:
The parity-check matrix H is divided into multiple sub-matrices, and the decoding process is segmented into multiple processing stages. Each stage handles a portion of the decoding computations, allowing the overall complex task to be broken down into manageable segments that can be processed in parallel or sequentially with reduced complexity at each step.
Solution Approach 2:
The patent introduces a time dimension by using pipelined processing architecture. Different stages of the decoding algorithm operate at different time steps, allowing multiple computations to overlap in time. This transforms the computational problem from a purely spatial arrangement into a temporal sequence, enabling higher throughput without proportionally increasing complexity.
2Device complexity
If computational complexity is reduced to simplify decoding, then device complexity is decreased, but memory requirements increase
Solution Approach 1:
The system pre-computes and stores certain intermediate results and lookup tables in memory before the actual decoding process begins. By performing these computations in advance and storing the results, the patent reduces the computational burden during real-time decoding while accepting increased memory usage to hold the pre-computed data.
Solution Approach 2:
The patent uses multiple copies of certain data structures and intermediate results stored in memory to avoid repeated computations. By maintaining redundant copies of critical information, the decoder can quickly access needed data without performing complex calculations, thus reducing computational complexity at the cost of increased memory storage.
3Reliability
If standard LDPC decoding architecture is used to ensure decoding accuracy, then reliability is maintained, but interconnection complexity increases
Solution Approach 1:
The patent combines multiple processing functions into integrated units that perform both computation and data movement in a unified architecture. By merging separate computation blocks and data transfer paths into combined processing elements, the patent reduces the number of individual interconnections needed while maintaining the same decoding functionality and accuracy.
Solution Approach 2:
The patent designs universal processing units that can perform multiple different functions depending on the operational phase. These multi-functional blocks replace several specialized components, thereby reducing the overall interconnection complexity. Each universal unit adapts its behavior based on control signals, eliminating the need for dedicated interconnections for each specific function.
Data Source
Figure 1A~1B
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AI summary
An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates.