LDPC Decoder Flag Memory Layout for Low-Power Iterative Decoding

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Solution Overview

Problem

Low-density parity-check (LDPC) decoding processes consume high power due to frequent memory access, and reducing memory access can compromise error correction performance.

Innovation Solution

A decoder architecture with a main memory and a smaller flag memory, where flag encoding and decoding operations determine whether to store data in the main memory or flag memory, optimizing power consumption without degrading error correction capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If memory access is reduced to save power, then power consumption decreases, but error correction performance deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoiderror correction performance

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent divides the intermediate value storage into two segments: a first memory for storing all intermediate values and a second memory for storing only flag data. This segmentation allows the system to reduce memory access operations by checking flags before full memory access, thereby reducing power consumption while maintaining error correction capability through selective access.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent extracts the critical error indication information (flags) from the complete intermediate value data and stores it separately in a dedicated second memory. This extraction allows the decoder to quickly check error status without accessing the entire intermediate value set, reducing unnecessary memory access operations and power consumption while preserving error detection and correction functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

2Use of energy by moving object

If the number of memory access operations is reduced, then power consumption decreases, but throughput decreases

Engineering Contradiction:

Improvepower consumptionVSAvoidthroughput

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent performs preliminary action by pre-calculating and storing flag data that indicates whether intermediate values require correction, before the actual decoding operation proceeds. This preliminary flag storage enables subsequent operations to skip unnecessary memory access steps, reducing both power consumption and maintaining throughput by avoiding redundant access operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces flag data as an intermediary element between the intermediate values and the decoding logic. This intermediary provides quick status information that mediates whether full memory access is necessary, allowing the system to reduce power-consuming access operations while maintaining throughput by quickly determining when access can be skipped.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11791846B2Decoder performing iterative decoding, and storage device using the same

Publication Date: 2023.10.17 SAMSUNG ELECTRONICS CO LTD

AI summary

A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.