LDPC Bit-Flipping Decoder Using Channel-Biased Flip Thresholds
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Solution Overview
Problem
Conventional bit-flipping decoding algorithms for LDPC codes in NAND flash storage devices are inefficient, consuming excessive power and failing to account for the reliability of input bits, leading to low correction performance and high read latency.
Innovation Solution
An enhanced bit-flipping decoding algorithm that incorporates channel inputs, an adaptable flipping criterion, and a heuristic flip threshold determination to improve correction performance and convergence rate, while reducing power consumption and decoding time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bit-flipping decoding algorithm is used, then implementation is simple, but correction performance is poor and read latency is high
Solution Approach 1:
The patent performs preliminary classification of bits into reliable and unreliable categories before decoding. By pre-identifying unreliable bits using channel input information, the decoder can focus computational efforts on these critical bits, improving correction performance while reducing overall decoding time and latency.
Solution Approach 2:
The patent applies different decoding strategies to different bits based on their reliability characteristics. Reliable bits are handled with simpler operations while unreliable bits receive more intensive processing. This localized differentiation improves overall correction performance without uniformly increasing complexity across all bits.
2Use of energy by stationary object
If conventional bit-flipping decoding algorithm is used, then computational complexity is low, but power consumption is excessive
Solution Approach 1:
The patent applies decoding efforts selectively rather than uniformly to all bits. By focusing computational resources on unreliable bits identified through channel input analysis, the system achieves adequate correction performance with reduced overall computational complexity and lower power consumption compared to processing all bits equally.
3Reliability
If conventional bit-flipping decoding algorithm is used, then algorithm is simple to implement, but it does not consider reliability of input bits
Solution Approach 1:
The patent performs preliminary classification of bits into reliable and unreliable categories using channel input information before the main decoding process. This pre-processing step enables the subsequent decoding algorithm to focus on unreliable bits, improving correction performance while keeping the overall complexity manageable through targeted rather than universal processing.
Data Source
AI summary
A bit flipping algorithm for an LDPC decoder evaluates a data sequence d with respect to a parity code matrix H. Where one or more checks fail, bits of d are flipped such that for some iterations, the bits are flipped with bias toward and original data sequence r. For example, for some iterations, where the number of failed checks are below a first threshold T1, bits are only permitted to flip back to the value of that bit in the original data sequence r. In such iterations, bits are permitted to flip from the value in the original data sequence r only when the number of failed checks is greater than a second threshold T2, T2>T1. Values for thresholds may be based on a number of flipped bits from a previous iteration and may be calculated using a syndrome s=Hd from a previous iteration.