LDPC Decoder Pipeline for High-Degree Variable Nodes
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Solution Overview
Problem
Current error correction methods in non-volatile memory devices, such as SSDs, face challenges in reducing latency and complexity while maintaining data integrity, particularly with multi-level NAND flash devices that require strong error-correction codes, leading to increased storage space for ECC parity bits.
Innovation Solution
The implementation of a pipeline architecture for decoding low-density parity-check (LDPC) codes, where low-weight columns are processed in a single time-step and high-weight columns in multiple time-steps, reduces read-latency and improves reliability by partitioning check nodes into sets and performing variable and check node updates in a specific order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strong error-correction codes are used to improve data reliability, then data integrity is improved, but storage space for ECC parity bits increases
Solution Approach 1:
The parity-check matrix columns are segmented into two groups: high-weight columns (first group) and low-weight columns (second group). This segmentation allows different processing strategies to be applied to different column types, optimizing both correction capability and resource usage. The high-weight columns provide strong error correction while the low-weight columns can be processed more efficiently with reduced hardware resources.
2Reliability
If traditional decoding methods are used to ensure thorough error correction, then correction capability is improved, but decoding latency increases
Solution Approach 1:
The decoding process uses dynamic time-step allocation based on column weight. High-weight columns are processed over multiple time-steps (first number of time-steps) while low-weight columns are processed in a single time-step (second number of time-steps). This dynamic approach adapts the decoding duration to the actual complexity of each column, reducing overall latency while maintaining thorough error correction for high-weight columns.
Solution Approach 2:
The method performs preliminary classification of columns into high-weight and low-weight groups before decoding begins. This preliminary action allows the decoder to prepare appropriate processing pipelines for each group, enabling low-weight columns to be quickly processed in parallel while high-weight columns receive more intensive processing, thereby optimizing the overall decoding timeline.
3Device complexity
If uniform processing is applied to all columns to simplify decoder design, then device complexity is reduced, but decoding efficiency decreases
Solution Approach 1:
The decoder implements local quality by applying different processing qualities to different column types. High-weight columns receive comprehensive multi-time-step processing with full error correction capability, while low-weight columns receive streamlined single-time-step processing. This local differentiation optimizes the balance between decoder complexity and decoding efficiency, as each column type receives processing appropriate to its specific characteristics.
Data Source
AI summary
Devices, systems and methods for improving decoding operations of a decoder are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising N columns, wherein each of at least B columns of the parity matrix has a column weight that exceeds a predetermined column weight, processing the N columns based on a message passing algorithm, and determining, based on the processing, a candidate version of the transmitted codeword, wherein the processing for each of the N columns comprises performing a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation on the first set and the second set, the read operation and the CNU operation on each of the at least B columns spanning two or more time-steps.