Column-Based LDPC Decoder Architecture for High Sub-Matrix Degrees

The decoder architecture is segmented into multiple processing units, each handling specific sub-matrices. The parity check matrix is divided into block rows and block columns, with each processing unit responsible for a specific segment. This segmentation allows the decoder to handle higher sub-matrix degrees by distributing the computational load across multiple units, resolving the contradiction between maintaining low complexity and increasing adaptability.

The patent introduces a new dimensional organization by arranging processing units in a two-dimensional array structure with row processors and column processors. This dimensional change allows the system to handle higher sub-matrix degrees by adding processing units in the appropriate dimension, thereby increasing adaptability without proportionally increasing overall complexity through efficient resource sharing.

The processing units are designed with universal functionality to handle multiple operations including syndrome calculation, bit flipping, and probability updates. Each processing unit can perform multiple functions depending on the decoding stage and sub-matrix degree requirements. This multi-functionality allows the decoder to achieve high reliability for various LDPC codes without proportionally increasing complexity, as the same hardware resources are reused across different operational modes.

The patent employs parameter changes by dynamically adjusting the number of processing units activated, the block size of sub-matrices, and the iteration count based on the specific LDPC code requirements. This allows the decoder to optimize the balance between reliability and complexity for different applications, achieving high bit error rate performance when needed while maintaining lower complexity for less demanding scenarios.

The iterative decoding algorithm implements periodic action by performing a fixed number of iterations with each iteration consisting of systematic steps: syndrome calculation, identification of failed parity checks, bit flipping selection, and probability updates. This periodic structure allows the decoder to achieve low bit error rates through multiple passes while controlling complexity by limiting the maximum iteration count and using efficient data structures that reset and reuse memory across iterations.

The decoding process maintains continuity of useful action by keeping all processing units actively engaged throughout each iteration, with pipelined execution of syndrome calculation, bit flipping, and probability updates. Data flows continuously through the processing units without idle periods, maximizing the utilization of hardware resources and achieving low bit error rates through sustained computational effort without proportionally increasing peak complexity.