Programmable LDPC Decoder Using Precomputed H-Matrix Control
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Solution Overview
Problem
Existing LDPC decoders are designed to decode specific standards and cannot handle variations in H-Matrices across different standards, leading to memory access conflicts and the need for hardware architecture changes to support multiple standards.
Innovation Solution
A multi-standard programmable LDPC decoder system that generates pre-computed control signals based on H-matrix analysis and stores them in on-chip memory, allowing for flexible processing of various H-Matrices without altering the hardware architecture, using a control signal generation unit, hardware decoder unit, and configurable hardware to handle different standards and code rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware logic is used to generate control signals based on H-Matrix structure, then decoding speed is improved, but adaptability to different standards deteriorates
Solution Approach 1:
Control signals are pre-computed offline based on H-Matrix attributes (block length, row weight, sub-matrix size, layer configuration) and stored in a control signal storage unit. This preliminary preparation allows the hardware decoder to operate at full speed without real-time computation overhead, while simultaneously enabling support for multiple standards by simply loading different pre-computed control signals corresponding to different H-Matrix configurations.
2Device complexity
If H-Matrix attributes are decoded by hardwired logic, then control signal generation is simplified, but support for multiple standards is lost
Solution Approach 1:
The hardware decoder is designed with a universal architecture that can support multiple LDPC standards (DVB-T2, DVB-S2, DVB-C2, 802.11, 802.3, 802.16, CDMB-T) through a single unified design. The system uses a control signal storage unit that can load different pre-computed control signals for different standards, allowing the same hardware block to perform multiple standard-specific decoding functions without requiring separate hardwired logic for each standard.
3Adaptability or versatility
If existing hardware architecture is modified to support new standards, then multi-standard capability is improved, but hardware complexity and reconfiguration requirements increase
Solution Approach 1:
All standard-specific configuration parameters are pre-computed offline and stored as control signals. When a new standard or code rate needs to be supported, only the pre-computed control signal table needs to be updated, not the hardware architecture itself. This separates the complexity of multi-standard support from the hardware design, maintaining a simple universal hardware structure while enabling flexible standard support through data configuration.
Data Source
AI summary
A method for implementing multi standard programmable low-density parity check decoder in a receiver is provided. The method includes (i) generating, by a control signal generation unit, pre computed control signals associated with a h-matrix, (ii) obtaining, by a control signal storage unit of a hardware decoder unit, the pre computed control signals associated with the h-matrix, (iii) obtaining, by a LLR memory fetch & data align unit, LLR bytes from a LLR memory unit, (iv) rotating, by a rotation and aligning unit, the LLR bytes to obtain aligned valid LLR bytes, (v) processing, by the processing element unit, the aligned valid LLR bytes to obtain an output data, and (vi) decoding, the h-matrix associated with at least one standard and code rates based on the pre computed control signals.