Non-Binary LDPC Decoder Scheduling to Cut Idle-Cycle Latency
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Solution Overview
Problem
Existing data decoding systems, particularly those using Low Density Parity Check (LDPC) codes, face delays due to idle cycles while waiting for message exchanges between variable nodes and check nodes, which increases decoding latency.
Innovation Solution
Implementing a low latency scheduling method that allows variable node updates to proceed using message vectors from previous iterations as soon as they are available, reducing idle cycles and enabling earlier processing without waiting for complete data from check node units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If variable node updates wait for complete message vectors from check node units, then decoding accuracy is maintained, but decoding latency increases due to idle cycles
Solution Approach 1:
The patent applies preliminary action by allowing variable node updates to proceed using previously available message vectors before the current iteration's complete message vectors are ready. The variable node unit performs updates in advance using stored historical message data, eliminating idle waiting cycles while maintaining decoding reliability through iterative refinement as new message vectors become available.
2Productivity
If variable node updates use message vectors from previous iterations early, then processing speed increases, but data consistency may be compromised
Solution Approach 1:
The patent implements dynamics by creating a flexible scheduling system where the variable node unit dynamically switches between using historical message vectors and current iteration message vectors. The system adapts its data source based on availability, allowing early processing with historical data while transitioning to current iteration data as it becomes available, thus maintaining data consistency without sacrificing processing speed.
Solution Approach 2:
The patent ensures continuity of useful action by eliminating idle cycles in the variable node unit. Instead of waiting for complete message vectors, the system continuously processes available data from previous iterations, maintaining uninterrupted processing flow. This continuous action preserves productivity while data consistency is maintained through the iterative nature of the decoding process where earlier results are refined over time.
Data Source
AI summary
Various embodiments of the present invention provide systems and methods for decoding of non-binary LDPC codes. For example, a low density parity check data decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node message vectors, a check node processor operable to perform check node updates and to generate the check node to variable node message vectors, and a scheduler operable to cause the variable node processor to use check node to variable node message vectors from multiple decoding iterations when performing the variable node updates for a given decoding iteration.