LDPC Decoder Circuit With Integrated Node Updates for Higher Throughput
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Solution Overview
Problem
In high-speed communication systems, LDPC decoders face increased hardware complexity and power consumption due to longer encoding lengths, which hinder decoding efficiency and throughput.
Innovation Solution
The proposed method integrates bit node message updates into check node operations, using check node input messages to generate new bit node messages, and employs a two-stage check node processor circuit to reduce memory size and power consumption, while enhancing decoding speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate check node processor and bit node processor are used with dedicated sum message memory, then decoding accuracy is maintained, but hardware area and complexity increase significantly
Solution Approach 1:
The patent combines the check node processor and bit node processor into a single integrated processor that can perform both functions. The processor alternates between executing check node processing instructions and bit node processing instructions, eliminating the need for separate dedicated processors and their associated sum message memories, thus reducing hardware area and complexity while maintaining decoding accuracy.
Solution Approach 2:
The integrated processor is designed as a universal processing unit capable of performing multiple functions - both check node processing and bit node processing. By using a single processor that can adaptively execute different types of processing instructions, the system avoids the hardware overhead of multiple specialized processors while preserving the functional capabilities needed for accurate decoding.
2Reliability
If separate sum message memory for check nodes and bit nodes is allocated, then message storage is ensured, but power consumption increases
Solution Approach 1:
The patent merges the separate sum message memories for check nodes and bit nodes into a single shared memory structure. The integrated processor manages memory access dynamically, allocating the shared memory to store sum messages based on the current processing phase (check node or bit node processing), thereby ensuring message storage requirements are met while reducing the total memory capacity needed and lowering power consumption.
3Reliability
If longer encoding length is used, then error correction capability is improved, but decoding efficiency and throughput decrease
Solution Approach 1:
The patent implements a dynamic processing architecture where the integrated processor can adaptively adjust its operation based on the encoding length and processing requirements. The processor dynamically switches between check node and bit node processing instructions in an alternating manner, optimizing the decoding process for different code lengths and maintaining high throughput even with longer encoding lengths that require more iterations.
Data Source
AI summary
An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.