Regular LDPC Decoder Architecture With Reduced Interconnect Complexity

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Solution Overview

Problem

Low density parity check (LDPC) decoders face complexity in interconnect issues and high computational requirements, particularly in parallel implementations, which hinders their efficiency in error correction for next-generation communication and data storage systems.

Innovation Solution

The proposed solution involves novel techniques for decoding LDPC codes, including the use of check node units (CNUs) with comparators to determine minimum values, cyclic shift characteristics, and log-likelihood ratio processing, which reduce message storage memory and routing logic, enabling simpler and more efficient decoding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If parallel LDPC decoder designs are used to improve decoding speed and performance, then productivity is improved, but device complexity increases due to complex interconnect issues

Engineering Contradiction:

Improvedecoding speedVSAvoidinterconnect complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The decoder is divided into multiple independent check node unit arrays, where each array processes a specific block row of the parity check matrix. This segmentation allows parallel processing of different blocks while reducing interconnect complexity within each array, as the units only need to communicate with variable node units rather than each other.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Variable node units act as intermediaries between check node units. Instead of check node units being directly interconnected, they communicate through variable node units, which simplifies the interconnect structure and reduces the complexity of message routing between check node units.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If more message storage memory is allocated to improve decoding accuracy, then reliability is improved, but device complexity and resource requirements increase

Engineering Contradiction:

Improvedecoding accuracyVSAvoidmemory requirements

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Each check node unit is equipped with local memory to store only the minimum values and their locations relevant to its specific processing tasks, rather than maintaining global message storage. This local memory approach reduces overall memory requirements while maintaining decoding accuracy through localized optimization.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The decoder uses iterative decoding where message values are updated and reused across multiple iterations. Previous message values are discarded and recovered in subsequent iterations, allowing the system to maintain high reliability with reduced memory storage by reusing computational results rather than storing all intermediate values.

Inventive Principle:

Principle #34Discarding and recovering

Data Source

PatentUS8656250B2Low density parity check decoder for regular LDPC codes

Publication Date: 2014.02.18 TEXAS A&M UNIVERSITY

AI summary

A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.