Programmable LDPC Decoder Interleaving for Throughput and Code Flexibility
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Solution Overview
Problem
Existing LDPC decoders are preconfigured to support only a limited number of LDPC codes, making them inflexible with the phased out older codes and proprietary codes, which limits their adaptability to new communication standards and increases hardware resource utilization due to data dependencies.
Innovation Solution
A programmable LDPC decoder with a repository that stores parity-check information for multiple codes, allowing dynamic configuration and reconfiguration to support a wide range of LDPC codes by interleaving data blocks across stages, thereby optimizing hardware resource utilization and adapting to different standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If LDPC decoders are preconfigured to support only a limited number of LDPC codes, then hardware resource utilization is reduced, but adaptability to new communication standards and support for proprietary codes deteriorates
Solution Approach 1:
The decoder is designed with a universal architecture that can support multiple LDPC codes through a repository storing parity-check information for different codes. The same hardware resources are reused across different code configurations, achieving multi-functionality without proportionally increasing hardware complexity
Solution Approach 2:
The decoder implements dynamic reconfiguration capability where the repository can be updated with new parity-check information for different LDPC codes. This allows the system to adapt to new communication standards and proprietary codes by loading appropriate parity-check matrices without permanent hardware changes
2Device complexity
If data blocks are processed sequentially without interleaving, then hardware resource utilization is reduced, but throughput deteriorates due to data dependencies
Solution Approach 1:
The data block is divided into multiple layers that can be processed independently and in parallel. By segmenting the processing into layers, the decoder can utilize multiple hardware resources simultaneously, increasing throughput while maintaining manageable hardware resource requirements
Solution Approach 2:
The interleaved processing architecture eliminates idle cycles by continuously utilizing hardware resources across different layers and data blocks. While one layer is being processed, other resources prepare or wait for the next layer, ensuring continuous productive action without wasted cycles
Data Source
AI summary
A decoder circuit can include low-density parity-check (LDPC) decoder circuitry having a plurality of stages and an LDPC repository configured to store parity-check information associated with one or more LDPC codes. The LDPC repository is configured to determine a stall requirement for a layer of a first data block and perform a memory check for a second data block. The LDPC repository, in response to the stall requirement indicating a stall for the layer of the first data block and determining that the memory check is satisfied, is further configured to schedule processing of the first data block and the second data block in the LDPC decoder circuitry using the parity-check information by interleaving the layer of the first data block and a layer of the second data block through the plurality of stages of the LDPC decoder circuitry.