LDPC Decoder Iteration Control for Severe Interference Frames

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Solution Overview

Problem

Fixed iteration limits in low-density parity-check (LDPC) decoders can lead to unsuccessful decoding of frames with severe interference, resulting in increased bit errors and reduced decoding efficiency.

Innovation Solution

A circuit and method that dynamically adjust the allowed maximum iteration count for each frame based on the successful decoding of previous frames, allowing for increased iterations when necessary to handle severe interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed iteration count is used for decoding, then decoding time is controlled within limits, but frames with severe interference cannot be successfully decoded

Engineering Contradiction:
Improvedecoding success rateVSAvoiddecoding throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies dynamics by making the iteration count adjustable rather than fixed. The control circuit dynamically modifies the allowed maximum iteration count for each frame based on channel conditions and decoding requirements, allowing the system to adapt between quick decoding for good frames and extended decoding for severe frames, thus resolving the contradiction between reliability and productivity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of iteration count from a static fixed value to a dynamic variable that can be modified based on frame characteristics and channel conditions. The control circuit adjusts this parameter in real-time, enabling the decoder to optimize between speed and success rate by changing the iteration limit parameter according to actual needs

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the allowed maximum iteration count is increased, then decoding capability for severe interference is enhanced, but decoding time increases

Engineering Contradiction:
Improvedecoding capabilityVSAvoiddecoding delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically adjusts the iteration count based on actual decoding needs rather than always using the maximum value. For frames with mild interference, fewer iterations are performed, reducing time loss. For frames with severe interference, the iteration count is increased to enhance decoding capability, thus resolving the time-capability trade-off

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control circuit proactively adjusts the iteration count before attempting to decode difficult frames by evaluating channel conditions and frame characteristics in advance. This preliminary adjustment ensures that sufficient iterations are allocated for severe frames while avoiding unnecessary iterations for easy frames, optimizing the balance between capability and time

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11329763B2Decoding method and associated circuit
Publication Date: 2022.05.10 REALTEK SEMICON CORP
  • US11329763B2 patent drawing
  • US11329763B2 patent drawing
  • US11329763B2 patent drawing

AI summary

A decoding method and associated circuit are provided. The circuit includes a first memory, a decoder and a control circuit. In operations of the circuit, the first memory is configured to receive a data stream; the decoder is configured to receive the data stream to sequentially generate a plurality of frames, and sequentially decode the plurality of frames to respectively generate a plurality of codewords; and the control circuit is configured to determine an allowed maximum iteration count for decoding a current frame according to an iteration count for successfully decoding at least one previous frame of the current frame.