Iterative LDPC Decoder Scheduling for Throughput and Error Correction
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Solution Overview
Problem
Existing iterative decoders face challenges in hardware implementation due to high complexity and cost, especially when performing multiple iterations, which affects throughput and reliability in storage systems, as they require duplication of detector and decoder blocks and are time-consuming in firmware implementation.
Innovation Solution
The method involves a hardware decoder that iteratively decodes data blocks with the option to perform additional iterations during idle times, using a soft output detector and LDPC decoder, and storing information in a local buffer for sequential or parallel/sequential updating of parity constraints, allowing full error correction capability and minimizing firmware data recovery procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple iterations are allowed in hardware decoder, then error correction capability is improved, but hardware complexity and cost increase significantly
Solution Approach 1:
The patent segments the decoding iterations into two distinct phases: a first set of iterations performed in hardware during the data read channel time, and a second set of iterations performed in hardware during idle time periods. This segmentation allows the system to achieve multiple iterations without requiring all iterations to be simultaneously available in hardware, thereby reducing hardware complexity while maintaining error correction capability.
Solution Approach 2:
The patent performs preliminary error correction by executing the first set of iterations in hardware during the data read channel time before the data is fully processed. This preliminary action reduces the burden on subsequent processing stages and allows the system to prepare corrected data in advance, improving overall system efficiency without requiring full error correction capability to be available at all times.
2Reliability
If more iterations are performed in hardware, then decoding accuracy is improved, but throughput is degraded due to time consumption
Solution Approach 1:
The patent maintains continuity of useful action by utilizing idle time periods in the hardware decoder for performing the second set of iterations. Instead of leaving the hardware decoder idle, the system continuously uses available time slots to perform additional decoding iterations, thereby improving decoding accuracy without significantly impacting throughput. The hardware decoder remains productive throughout the data processing cycle.
Solution Approach 2:
The patent introduces dynamic scheduling of decoding iterations based on the actual time available in the data read channel and idle time periods. The system dynamically adjusts when and how many iterations to perform in hardware versus firmware, optimizing the balance between decoding accuracy and throughput based on real-time system conditions and data requirements.
3Reliability
If full redundancy decoding is used in hardware, then error correction capability is improved, but hardware complexity increases
Solution Approach 1:
The patent makes the hardware decoder universal by designing it to perform multiple functions: executing the first set of iterations during data read channel time and the second set of iterations during idle time periods. This multi-functionality allows the same hardware resources to provide full error correction capability across different time slots, eliminating the need for dedicated hardware for each iteration set and thereby reducing overall hardware complexity.
Solution Approach 2:
The patent changes the operational parameters of the hardware decoder by varying the number and timing of iterations performed in hardware versus firmware. Instead of fixing the iteration count and location, the system dynamically adjusts these parameters based on data quality, time availability, and system load, allowing full error correction capability to be achieved with optimized hardware utilization.
4Reliability
If iterative decoding is implemented in firmware, then full error correction capability is achieved, but processing time increases significantly
Solution Approach 1:
The patent performs preliminary error correction by executing the first set of iterations in hardware during the data read channel time, before firmware processing is required. This preliminary hardware-based correction reduces the amount of work needed in firmware, thereby achieving full error correction capability while minimizing the time loss associated with firmware processing.
Data Source
AI summary
An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.