Bit-Flipping LDPC Decoder with Iteration Selection for Fast Convergence
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face challenges in efficiently decoding Low-Density Parity-Check (LDPC) codes due to high computational complexity and limited convergence speed, particularly in high-speed applications where fast and low-complexity error control coding is required.
Innovation Solution
The implementation of a memory system with a controller that performs a two-bit weighted bit-flipping algorithm and a column-layered group shuffled bit-flipping algorithm, using iterative operations based on variable and check nodes to optimize decoding, including a second flipping function operation to estimate flipping necessity and frequency, and a first flipping operation to correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional LDPC decoding methods are used, then error correction capability is provided, but computational complexity is high and convergence speed is limited
Solution Approach 1:
The patent segments the LDPC decoding process into two distinct parts: a syndrome decoding step that processes parity check equations, and a bit-flipping decoding step that corrects errors based on syndrome results. This segmentation allows each step to be optimized independently, reducing overall computational complexity while maintaining decoding speed
Solution Approach 2:
The patent introduces syndrome values as an intermediary between the received codeword and the bit-flipping operation. The syndrome decoding generates intermediate syndrome values that guide the subsequent bit-flipping process, thereby reducing the direct computational burden on the main decoding algorithm
2Speed
If high-speed decoding is implemented, then convergence speed improves, but computational complexity increases
Solution Approach 1:
The patent performs preliminary syndrome decoding before the main bit-flipping iteration. By pre-processing the parity check equations and generating syndrome values in advance, the system accelerates the convergence of the subsequent decoding steps without proportionally increasing overall computational complexity
Data Source
AI summary
A memory system includes a memory device and a controller. The memory device outputs a codeword read from plural memory cells in response to a request. The controller is configured to establish a plurality of variable nodes and a plurality of check nodes from the codeword, perform a second flipping function operation for estimating flipping necessity and flipping frequency regarding the plurality of variable nodes based on the plurality of check nodes, determine, based on the flipping necessity and the flipping frequency, which iterative operation is performed during a first flipping operation for decoding the codeword, and perform the first flipping operation through a determined iterative operation to obtain the plurality of variable nodes.