Multi-Channel LDPC Decoder Layout for Faster Iterative Convergence
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Solution Overview
Problem
Current LDPC decoders face inefficiencies in throughput due to sequential processing of check nodes and bit nodes, which limits convergence speed and decoding iterations, especially for LDPC codes where check nodes in a group are connected to the same bit node.
Innovation Solution
A multi-channel decoder system with a hybrid LDPC decoder that processes groups of check nodes in parallel, allowing simultaneous updating of bit nodes within an iteration, enabling faster convergence and increased throughput by using extrinsic messages from previous check node groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If check nodes and bit nodes are processed sequentially in traditional LDPC decoders, then the decoding process is simpler to implement, but the convergence speed is slower and throughput is reduced
Solution Approach 1:
The decoder architecture is segmented into multiple independent processing channels, each capable of processing check nodes and bit nodes in parallel. The parity check matrix is divided into multiple sub-matrices, with each channel handling a specific sub-matrix. This segmentation enables simultaneous processing of multiple check nodes without increasing the complexity of individual processing units, thereby improving convergence speed while maintaining manageable device complexity.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by organizing check nodes into multiple channels that can operate simultaneously. Instead of processing check nodes sequentially in a single dimension, the architecture extends to multiple dimensions by creating independent processing paths. This dimensional expansion allows multiple check nodes to be processed in parallel, significantly improving convergence speed without proportionally increasing the complexity of each processing element.
2Productivity
If multiple check nodes are processed in parallel, then throughput is increased, but the decoder complexity increases due to additional processing channels
Solution Approach 1:
Each processing channel is designed as a universal unit capable of handling multiple functions: processing check nodes, updating bit nodes, and generating extrinsic messages. The channels use identical processing logic and data structures, allowing them to be replicated without increasing the complexity of individual units. This universality enables throughput scaling by simply adding more identical channels rather than designing increasingly complex single-channel processors.
Solution Approach 2:
The patent implements parallel processing by creating multiple copies of the same processing channel. Each channel is an identical replica that processes a specific subset of check nodes independently. This copying approach increases throughput linearly with the number of channels while keeping the complexity of each copy manageable and identical to the others, making the system scalable and easier to implement compared to designing entirely different processing units for each channel.
3Loss of time
If bit node updates wait for all check nodes to complete processing, then data consistency is maintained, but the decoding iteration time increases
Solution Approach 1:
The patent implements preliminary action by allowing bit node updates to occur as soon as their required check node processing is complete, rather than waiting for all check nodes in the iteration. Extrinsic messages are generated and used for updates in advance, enabling overlapping of check node processing and bit node update operations. This preliminary execution of updates reduces iteration time while maintaining data consistency through careful management of message passing and dependency tracking.
Solution Approach 2:
The architecture enables continuous useful action by eliminating idle waiting periods in the decoding process. While check nodes are being processed, bit nodes continuously receive and process available extrinsic messages without interruption. This continuous operation ensures that no processing element remains idle, maximizing resource utilization and reducing overall iteration time while maintaining data consistency through synchronized message passing protocols.
Data Source
AI summary
A multi-channel decoder system has a decoder core at least a portion of which is configurable as a LDPC decoder that, during decoding processing, divides check nodes of a node representation of a LDPC code into a plurality of groups, and, during an iteration, sequentially processes the groups while processing in parallel the check nodes within each group, thus improving decoding throughput.