LDPC Decoder Layer Mapping for Lower Hardware Complexity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current LDPC decoding methods require significant hardware resources and high costs due to the use of row-level parallel solutions for large check matrices, especially in 5G technologies, leading to inefficiencies and resource wastage.
Innovation Solution
A data processing method that utilizes a layered normalized min-sum decoding algorithm with a reduced number of variable nodes based on a base matrix, where nodes are mapped to valid submatrices in each layer of the check matrix, reducing hardware requirements by using a raptor-like structure and minimizing the number of nodes needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If row-level parallel solution is used for LDPC decoding, then decoding speed is improved, but hardware resources and costs increase significantly
Solution Approach 1:
The check matrix is segmented into multiple layers, and each layer is processed separately in the layered decoding algorithm. This segmentation allows the decoder to process one layer at a time, reducing the number of variable nodes and check nodes needed simultaneously, thereby reducing hardware resources while maintaining decoding speed
Solution Approach 2:
The patent uses dynamic mapping of variable nodes to valid submatrices in each layer. The number of active variable nodes changes dynamically depending on the layer being processed, allowing the hardware to be reused across different layers rather than requiring static allocation for all nodes simultaneously
2Reliability
If check matrix size is increased, then code performance is improved, but hardware resources required increase
Solution Approach 1:
Large check matrices are divided into multiple smaller layers, where each layer contains a subset of the check nodes. This allows the decoder to handle large code matrices for better performance while only activating the necessary subset of nodes for each layer, reducing simultaneous hardware requirements
Solution Approach 2:
The patent activates only the variable nodes and check nodes that are relevant to the current layer being processed, rather than activating all nodes in the large check matrix. This partial action approach maintains code performance through proper matrix design while reducing hardware resource usage at any given time
Data Source
Figure 1-1
Figure 1-2
Figure 1-3
AI summary
Embodiments of this application disclose a data processing method and a decoder, to decode a code word sequence. The method includes: receiving a code word sequence whose digit quantity is n (201); determining a check matrix of an order m×n, where a base matrix of the check matrix is a matrix of an order mb×nb (202); setting L variable nodes based on the base matrix (203), where L is greater than or equal to a quantity of values not equal to -1 in a row with a maximum quantity of values not equal to -1 in the base matrix; separately mapping valid submatrices in each of the check node to the L variable nodes (204); sending, to each of the L mapped variable nodes, data corresponding to each valid submatrix in each layer of the check matrix; and performing a corresponding operation step in a layered normalized min-sum decoding algorithm by the L variable nodes by using the received data (205).