LDPC Decoder Layered Architecture for Lower Memory and Routing Complexity
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Solution Overview
Problem
Low density parity check (LDPC) decoders face complexity in interconnect issues and require significant computational resources, limiting their efficiency in error correction for next-generation communication and data storage systems.
Innovation Solution
The development of novel techniques for decoding LDPC codes, including the use of check node units (CNUs) with comparators for comparing stored minimum values to received messages, and the application of log-likelihood ratios (LLRs) in a layered decoding architecture with cyclic shifts, reduces message storage memory and routing logic, enabling more efficient processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LDPC decoding methods are used, then error correction capability is achieved, but computational complexity and interconnect issues increase
Solution Approach 1:
The LDPC decoder is divided into multiple check node units (CNUs), each responsible for processing specific check nodes. Each CNU contains a minimal set of comparators (fewer than the check node degree) and storage elements, segmenting the overall decoding function into independent, low-complexity processing units that reduce interconnect complexity while maintaining error correction capability
Solution Approach 2:
Instead of implementing full comparator logic for all check node degrees, the patent uses a reduced set of comparators in each CNU. The comparators process only the necessary minimum values (typically the two smallest values) required for belief propagation decoding, eliminating excessive computational operations while preserving decoding accuracy
2Productivity
If parallel LDPC decoder designs are used, then decoding speed is improved, but interconnect complexity increases
Solution Approach 1:
The parallel decoder architecture is segmented into independent check node units that process different portions of the parity check matrix. Each CNU operates autonomously with local comparators and storage, minimizing the need for complex interconnect routing between processing elements while enabling parallel execution for high throughput
Solution Approach 2:
Each check node unit is designed with localized resources (comparators and storage elements) tailored to its specific processing requirements. The number of comparators in each CNU is optimized based on the local check node degree, creating non-uniform local quality that reduces overall interconnect complexity while maintaining parallel processing capability
3Measurement precision
If more comparators are used in check node units, then minimum value determination accuracy is improved, but the number of comparators exceeds the check node degree
Solution Approach 1:
The patent implements only the partial action necessary for accurate minimum value determination. Since belief propagation decoding requires only the two smallest values from the check node inputs, each CNU contains exactly enough comparators to identify these minimum values, avoiding the excessive use of comparators that would process all possible value combinations
Data Source
AI summary
A method and system for decoding low density parity check (LDPC) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.