LDPC Decoder Layered Parallel Processing for Faster Convergence
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Solution Overview
Problem
Existing gigabit LDPC decoding methods face inefficiencies due to high power consumption and slower convergence in meeting throughput requirements, primarily because they rely on flooding decoding which ignores contentions between check nodes, leading to increased iterations and power usage.
Innovation Solution
The proposed solution involves a receiver architecture with a low-density parity-check (LDPC) decoder that supports LDPC H matrix codes for Z=42 and Z=24, utilizing a layered decoding method that processes multiple rows simultaneously, reducing iterations and power consumption by addressing contentions between check nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flooding decoding is used to process LDPC codes, then parallel processing capability is improved, but power consumption increases and convergence speed decreases
Solution Approach 1:
The LDPC decoder is segmented into multiple processing elements (PEs), each responsible for decoding specific rows of the parity check matrix. This segmentation enables parallel processing while allowing each PE to operate independently with optimized resource allocation, reducing overall power consumption compared to a monolithic flooding decoder.
Solution Approach 2:
The system dynamically selects and processes only the necessary rows of the parity check matrix in each iteration based on convergence criteria. This dynamic approach allows the decoder to adapt the processing workload, reducing power consumption when fewer iterations are needed while maintaining high parallel processing capability when more iterations are required.
2Productivity
If flooding decoding is used to process LDPC codes, then parallel processing capability is improved, but convergence speed decreases
Solution Approach 1:
By dividing the parity check matrix into multiple rows assigned to different processing elements, the system achieves true parallel processing where multiple rows are decoded simultaneously in each iteration. This segmentation strategy maintains high parallel processing capability while reducing the total number of iterations needed for convergence.
Solution Approach 2:
The system performs preliminary organization of the parity check matrix rows and pre-allocates processing elements to specific rows before decoding begins. This preliminary action optimizes the parallel processing structure, enabling faster convergence by ensuring that all necessary parallel operations are set up and executed efficiently from the first iteration.
3Productivity
If multiple rows of parity check matrix are processed simultaneously, then decoding efficiency is improved, but processing complexity increases
Solution Approach 1:
The processing complexity is managed by segmenting the decoder into multiple independent processing elements, each handling a specific row of the parity check matrix. This segmentation allows parallel processing of multiple rows while keeping the complexity of each individual PE manageable and comparable to traditional single-row decoders.
Solution Approach 2:
Each processing element is designed as a universal unit capable of processing any row of the parity check matrix with the same operational logic. This multi-functionality approach allows the system to process multiple rows in parallel using identical processing structures, improving decoding efficiency without proportionally increasing processing complexity.
Data Source
AI summary
A receiver for use in a wireless communications network capable of decoding encoded transmissions. The receiver comprises receive path circuitry for receiving and downconverting an incoming radio frequency (RF) signal to produce an encoded received signal; and a low-density parity check (LDPC) decoder associated with the receive path circuitry for decoding the encoded received signal. The LDPC decoder further comprises a memory for storing a parity check H matrix comprising R rows and C columns, where each element of the parity check H matrix comprises one of a shift value or a −1 value; and a plurality of processing elements for performing LDPC layered decoding, wherein at least one processing element is operable to process in the same cycle a first row and a second row of the parity check H matrix.