LDPC Decoder Layout for Lower Clock Speed and Signal Complexity
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Solution Overview
Problem
Current LDPC decoders for high-speed applications like 25G PON require fast clock speeds and high power consumption due to the use of multiple parallel minimum-sum computing engines, leading to placement and routing challenges in integrated circuits.
Innovation Solution
The LDPC decoder is designed with a parity check code storage block and computing engines arranged in a checkerboard pattern, with column groups closer to the center and buffer zones between engines, allowing up to 256 engines to operate at a reduced clock speed and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple parallel minimum-sum computing engines are used to achieve decoding, then the clock speed requirement is reduced, but the number of signals in the circuit increases excessively
Solution Approach 1:
The parity check code matrix is divided into multiple column groups, with each column group processed by a dedicated computing engine. This segmentation allows the use of multiple parallel computing engines (e.g., 64 engines for 25G PON) while organizing signals in a manageable structure, reducing the overwhelming signal complexity that would result from processing the entire matrix at once.
Solution Approach 2:
The patent introduces a two-dimensional arrangement of computing engines positioned on both sides of the parity check code storage block. This spatial dimensionality change allows engines to access storage blocks in parallel, reducing the clock speed requirement while keeping signal complexity manageable through organized signal paths.
2Speed
If 256 parallel minimum-sum computing engines are used to achieve decoding, then the clock speed requirement is significantly reduced, but placement and routing becomes extremely difficult
Solution Approach 1:
The system processes the parity check code matrix by dividing it into column groups, with each computing engine handling a specific column group. This segmentation makes the placement and routing of 256 computing engines feasible by organizing them in a structured manner around the storage block, rather than requiring random interconnections.
Solution Approach 2:
Computing engines are arranged in a two-dimensional configuration on both sides of the storage block, creating a scalable and manufacturable layout. This spatial organization simplifies placement and routing compared to a linear arrangement, making it practical to implement 256 engines while maintaining manageable signal complexity.
3Device complexity
If 64 minimum-sum computing engines are used, then the number of signals becomes manageable, but the clock speed requirement remains high at around 1 GHz
Solution Approach 1:
The patent employs a dynamic architecture where computing engines can be configured to process different column groups based on the specific decoding requirements. This flexibility allows the system to scale the number of engines dynamically, enabling the use of 256 engines for applications requiring lower clock speeds without being constrained by fixed signal complexity limitations.
Solution Approach 2:
The two-dimensional arrangement of computing engines on both sides of the storage block enables parallel processing of multiple column groups simultaneously. This spatial configuration increases the effective processing capacity, allowing the system to use more engines (256 instead of 64) while keeping signal complexity manageable, thereby reducing the clock speed requirement.
Data Source
AI summary
An LDPC decoder includes a parity check code storage block and a plurality of computing engines. The parity check code storage block is configured to store a parity check code matrix. The parity check code matrix includes a plurality of columns. Each of the columns includes a plurality of submatrices. The parity check code storage block includes a plurality of column group storage blocks. Each of the column group storage blocks is configured to store a column group including one or more of the columns. The column group storage block which stores the column group including one or more of the columns is disposed closer to the center of the parity check code storage block. The computing engines are disposed on two sides of the parity check code storage block.