LDPC Decoder Memory Layout for Buffer-Free LLR Reordering
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Solution Overview
Problem
Existing Low Density Parity Check (LDPC) codes are not widely adopted due to their complex encoding and decoding processes, which require large memory storage and additional logic circuitry, making them inefficient for practical implementation in communication systems.
Innovation Solution
A memory-efficient LDPC decoder is implemented by eliminating memory buffers associated with log-likelihood-ratio (LLR) data bits reordering, de-reordering, and demapping procedures, and combining these operations into single stages to reduce memory storage and logic circuitry requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LDPC decoding procedures (reordering, de-reordering, and demapping) are implemented with separate memory buffers, then decoding accuracy is maintained, but memory storage requirements and die-size increase significantly
Solution Approach 1:
The patent combines reordering, de-reordering, and demapping operations into a single integrated stage that processes LLR data bits in one pass. This merging eliminates the need for separate memory buffers for each operation, reducing memory storage requirements while maintaining decoding accuracy through coordinated processing of the same data stream
Solution Approach 2:
The integrated stage performs multiple functions simultaneously: it reorders LLR bits according to the LDPC code structure, de-reorders them for decoding, and demaps them to output bits. This multi-functional approach replaces multiple specialized memory buffers with a single versatile processing unit, reducing overall memory requirements
2Adaptability or versatility
If traditional LDPC decoding procedures are implemented with separate memory buffers and logic circuitry, then decoding functionality is complete, but die-size and power consumption increase
Solution Approach 1:
The patent merges reordering, de-reordering, and demapping logic circuitry into a single integrated processing stage. This consolidation reduces the total number of separate logic blocks and interconnections required, thereby reducing die-size while maintaining complete decoding functionality through the combined operations
Solution Approach 2:
The integrated stage is designed to process LLR data bits in a segmented fashion, handling reordering, de-reordering, and demapping operations on different portions of the data stream within the same processing unit. This segmentation allows the circuit to maintain full functionality while using a compact, unified structure rather than multiple large separate blocks
Data Source
AI summary
A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.